SLVSES8A October   2020  – December 2020 LM5127-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Enable (EN, VCC_HOLD)
      2. 8.3.2  Dual Input VCC Regulator (BIAS, VCCX, VCC)
      3. 8.3.3  Dual Input VDD Switch (VDD, VDDX)
      4. 8.3.4  Device Configuration and Light Load Switching Mode Selection (CFG/MODE)
      5. 8.3.5  Fixed or Adjustable Output Regulation Target (VOUT, FB)
      6. 8.3.6  Overvoltage Protection (VOUT, FB)
      7. 8.3.7  Power Good Indicator (PGOOD)
      8. 8.3.8  Programmable Switching Frequency (RT)
      9. 8.3.9  External Clock Synchronization (SYNC)
      10. 8.3.10 Programmable Spread Spectrum (DITHER)
      11. 8.3.11 Programmable Soft Start (SS)
      12. 8.3.12 Fast Re-start using VCC_HOLD (VCC_HOLD)
      13. 8.3.13 Transconductance Error Amplifier and PWM (COMP)
      14. 8.3.14 Current Sensing and Slope Compensation (CSA, CSB)
      15. 8.3.15 Constant Peak Current Limit (CSA, CSB)
      16. 8.3.16 Maximum Duty Cycle and Minimum Controllable On-time Limits (Boost)
      17. 8.3.17 Bypass Mode (Boost)
      18. 8.3.18 Minimum Controllable On-time and Minimum Controllable Off-time Limits (Buck)
      19. 8.3.19 Low Dropout Mode for Extended Minimum Input Voltage (Buck)
      20. 8.3.20 Programmable Hiccup Mode Overload Protection (RES)
      21. 8.3.21 MOSFET Drivers and Hiccup Mode Fault Protection (LO, HO, HB)
      22. 8.3.22 Battery Monitor (BMOUT, BMIN_FIX, BMIN_PRG)
      23. 8.3.23 Dual-phase Interleaved Configuration for High Current Supply (CFG)
      24. 8.3.24 Thermal Shutdown Protection
      25. 8.3.25 External VCCX Supply Reduces Power Dissipation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Status
        1. 8.4.1.1 Shutdown Mode
        2. 8.4.1.2 Configuration Mode
        3. 8.4.1.3 Active Mode
        4. 8.4.1.4 Sleep Mode
        5. 8.4.1.5 Deep Sleep Mode
          1. 8.4.1.5.1 Cutting Leakage Path in Deep Sleep Mode (DIS, SLEEP1, SENSE1)
        6. 8.4.1.6 VCC HOLD Mode
      2. 8.4.2 Light Load Switching Mode
        1. 8.4.2.1 Forced PWM (FPWM) Operation
        2. 8.4.2.2 Diode Emulation (DE) Operation (Connect RSS at SS)
        3. 8.4.2.3 Forced Diode Emulation Operation in FPWM Mode
        4. 8.4.2.4 Skip Mode Operation
      3. 8.4.3 LM5127 Cheat Sheet
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Recommended Power Tree Architecture
        2. 9.2.2.2 Application Ideas
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

Typical values correspond to TJ=25°C. Minimum and maximum limits apply over TJ=-40°C to 125°C. Unless otherwise stated, VBIAS = 12 V, RT = 9.09 kΩ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT(BIAS, VCCX, VDDX)
IBIAS-SD BIAS current in shutdown (VCCX=0V) VEN1 = 0 V, VEN2 = 0 V, VEN3 = 0 V, VVCC_HOLD = 0 V 2.8 4.5 µA
IBATTERY-SLEEP Battery drain in deep sleep mode (VBATTERY = 12 V, VCCX = 5 V (CH2), VDDX = 3.3 V (CH3), Non-switching) VEN1 = 2.5 V, VEN2 = 2.5 V, VEN3 = 2.5 V, CH1 boost mode 33 µA
VEN1 = 0 V, VEN2 = 2.5 V, VEN3 = 2.5 V, CH1 boost mode 22 µA
VEN1 = 0 V, VEN2 = 2.5 V, VEN3 = 0 V, CH1 boost mode 20 µA
VEN1 = 0 V, VEN2 = 0 V, VEN3 = 2.5 V, CH1 boost mode 14 µA
VEN1 = 2.5 V, VEN2 = 2.5 V, VEN3 = 2.5 V, CH1 buck mode 32 µA
IBIAS-SLEEP1 BIAS current in sleep mode (VDDX = 3.3 V, VCCX = 5 V) VEN1 = 2.5 V, VEN2 = 2.5 V, VEN3 = 2.5 V, CH1 boost mode 2.0 µA
IBIAS-SLEEP2 BIAS current in sleep mode (VDDX = 0 V, VCCX = 0 V) VEN1 = 0 V, VEN2 = 0 V, VEN3 = 0 V, VVCC_HOLD = 2.5 V, CH1 buck mode 25 38 µA
IVDDX-SLEEP VDDX current in sleep mode (VDDX = 3.3 V, VCCX = 0 V) VEN1 = 2.5 V, VEN2 = 2.5 V, VEN3 = 2.5 V, CH1 boost mode 100 115 µA
IBIAS-ACTIVE1 BIAS current in active mode (VCCX = 0 V) VEN1 = 2.5 V, VEN2 = 2.5 V, VEN3 = 2.5 V, CH1 boost mode 3300 3900 µA
VEN1 = 2.5 V, VEN2 = 2.5 V, VEN3 = 0 V, CH1 boost mode 2400 2850 µA
VEN1 = 2.5 V, VEN2 = 0 V, VEN3 = 0 V, CH1 buck mode 1700 2000 µA
IBIAS-ACTIVE2 BIAS current in active mode (VCCX = 5 V) VEN1 = 2.5 V, VEN2 = 2.5 V, VEN3 = 2.5 V, CH1 boost mode 125 175 µA
VEN1 = 2.5 V, VEN2 = 2.5 V, VEN3 = 0 V, CH1 boost mode 125 175 µA
VEN1 = 2.5 V, VEN2 = 0 V, VEN3 = 0 V, CH1 buck mode 125 175 µA
ENABLE(EN1, EN2, EN3)
VEN-RISING Enable threshold (ENx) EN rising 2 V
VEN-FALLING Enable threshold(ENx) EN falling 0.4 V
SLEEP1 in BOOST, BMIN_PRG in Buck
VSLEEP1-FALLING SLEEP1/BMIN_PRG threshold SLEEP1 falling 0.95 1 1.05 V
VSLEEP1-HYS SLEEP1/BMIN_PRG hysteresis SLEEP1 rising 15 mV
ISLEEP1 Hysteresis current (current sink) 30 µA
tD-WAKE1 Wakeup delay SENSE1 falling to DIS falling 5 µs
BMIN_FIX in Buck
VBMIN_FIX-FALLING BMIN_FIX threshold BMIN_FIX falling 5.415 5.7 5.985 V
VBMIN_FIX-RISING BMIN_FIX threshold BMIN_FIX rising 5.7 6.0 6.3 V
IBMIN_FIX BMIN_FIX bias current VBMIN1 = 12 V 1 3 µA
VCC and VCCX
VVCC-REG VCC regulation VBIAS = 7.0 V, IVCC = 250 mA 4.75 5 5.25 V
VCC regulation VBIAS = 7.0 V, no load 4.75 5 5.25 V
VCC regulation during dropout VBIAS = 3.8 V, IVCC = 250 mA 3.42 V
VVCC-UVLO-RISING VCC UVLO threshold VCC rising 3.55 3.65 3.75 V
VVCC-UVLO-FALLING VCC UVLO threshold VCC falling 3.2 3.3 3.4 V
IVCC-CL VCC sourcing current limit VCC = 4 V 250 mA
VVCCX-RISING VCCX transition threshold VCCX rising 4.2 4.3 4.4 V
VVCCX-FALLING VCCX transition threshold VCCX falling 4.0 4.1 4.2 V
VCCX to VCC dropout VVCCX = 4.5 V, IVCC = 250 mA 4.2 V
VDD and VDDX
VVCC-REG VDD regulation VBIAS = 7.0 V, No load at VCC, VCCX=GND 4.75 5 5.25 V
VVDD-UVLO-RISING VDD UVLO threshold VDD rising 3.0 3.1 3.2 V
VVDD-UVLO-FALLING VDD UVLO threshold VDD falling 2.9 3 3.1 V
SYNC/DITHER/VCC_HOLD
VSYNC-RISING SYNC threshold/SYNC detection threshold SYNC rising 2 V
VSYNC-FALLING SYNC threshold SYNC falling 0.4 V
Minimum SYNC pulse width 100 ns
IDITHER Dither source/sink current 16 20 24.5 µA
ΔfSW1 fSW Modulation (Upper Limit) +7 %
ΔfSW2 fSW Modulation (Lower Limit) -7 %
VDITHER-FALLING Dither disable threshold 0.65 0.75 0.85 V
RT
VRT RT regulation 0.5 V
DISCONNECTION(DIS), BATTERY MONITOR OUTPUT(BMOUT)
rDIS DIS pulldown switch rDS(on) 17 34 Ω
SS
ISS1 Soft-start current SS < 1.0 V 17 20 23 µA
ISS2 Soft-start current SS>1.5V 2 µA
rSS-PD SS pulldown switch rDS(on) 50 93 Ω
VSS-DONE MODE transition SS rising 1.5 V
VSS-DIS SS discharge detection threshold 50 75 105 mV
PULSE WIDTH MODULATION(PWM)
fSW1 Switching frequency RT = 220 kΩ 85 100 115 kHz
fSW2 Switching frequency RT = 9.09 kΩ 1980 2200 2420 kHz
tON-MIN-BUCK Minimum controllable on-time (HO on-time in Buck) RT = 9.09 kΩ 12 20 31 ns
tOFF-MIN-BUCK Minimum HO off-time during dropout (Buck) RT = 9.09 kΩ 85 110 150 ns
tON-MIN-BOOST Minimum controllable on-time
(LO on-time in Boost)		 RT = 9.09 kΩ 25 ns
tOFF-MIN-BOOST Minimum controllable off-time
(LO off-time in Boost)		 RT = 9.09 kΩ 70 90 118 ns
DMAX-BOOST1 Maximum duty cycle limit in Boost mode RT = 220kΩ 90 94 98 %
DMAX-BOOST2 Maximum duty cycle limit in Boost mode RT = 9.09 kΩ 75 80 83 %
Max pulse skip in low dropout mode 16 cycles
LOW IQ SLEEP MODE
VWAKE-FB FB wakeup threshold In reference to VREF –1 %
VWAKE-COMP COMP wakeup threshold 316 mV
tD-WAKE2 Wake-up delay RT = 9.09 kΩ 4.4 µs
VMINCLTH Minimum peak current in skip mode Current sense input 10 mV
CURRENT SENSE (CSPx, CSNx)
VSLOPE Peak slope compensation amplitude RT = 220 kΩ, in reference to CS inputs 80 mV
ACS Current sense amplifier gain 10 V/V
VCLTH1 Positive peak current limit threshold (CS input) CSBx = 3.3 V in Buck 52 60 68 mV
VCLTH2 Positive peak current limit threshold (CS input) CSBx = 0 V in Buck 48 60 69 mV
ICSA CSA bias current 1 µA
ICSB CSB bias current 120 µA
CS amplifier switch over 2.5 V
HICCUP MODE PROTECTION (RES)
Fault counter timeout 256 cycles
Normal cycles to reset fault counter 8 cycles
IRES RES current source 16 20 24 µA
VRESTH RES threshold 0.95 1.0 1.05 V
RRES RES pulldown switch rDS(on) 20 40 Ω
VRES-DIS RES discharge detection 100 mV
ERROR AMPLIFIER (COMPx, FBx)
VOUT-REG1 VOUT regulation (3.3 V) 3.26 3.3 3.34 V
VOUT-REG2 VOUT regulation (5.0V) 4.94 5.0 5.06 V
VREF Error amplifier reference In Boost 0.788 0.8 0.812 V
VREF Error amplifier reference In Buck 0.792 0.8 0.808 V
Gm Transconductance 1 mA/V
ISOURCE-MAX Maximum COMP sourcing current VCOMP = 0 V 80 µA
ISINK-MAX Maximum COMP sinking current VCOMP = 2.2 V 80 µA
VCLAMP-MAX COMP clamp voltage COMP rising 2.6 V
VOFFSET COMP to PWM input offset 0.264 0.300 0.336 V
VFB-SS Internal FB to SS clamp VFB = 0 V 80 115 mV
PGOOD, OVP
VOVTH-RISING Overvoltage threshold (OVP in Buck) FB rising (In reference to VREF) 105 107 109 %
VOVTH-FALLING Overvoltage threshold (OVP in Buck) FB falling (In reference to VREF) 103 105 107 %
VUVTH-RISING Undervoltage threshold FB rising (In reference to VREF) 93 95 97 %
VUVTH-FALLING Undervoltage threshold FB falling (In reference to VREF) 91 93 95 %
PGOOD deglich filter Both edges 23 µs
RPGOOD PGOOD pulldown switch RDSON 42 82 Ω
MOSFET DRIVER, SENSE1
VHO-H High-state voltage drop (HO driver) 100-mA sinking 0.1 0.15 V
VHO-L Low-state voltage drop (HO driver) 100mA sourcing 0.05 0.1 V
VLO-H High-state voltage drop (LO driver) 100-mA sinking 0.1 0.15 V
VLO-L Low-state voltage drop (LO driver) 100-mA sourcing 0.05 0.1 V
VHB-UVLO-FALLING HB-SW UVLO threshold HB-SW falling 2.2 2.50 2.75 V
IHB-SLEEP HB quiescent current in sleep HB-SW = 5 V 3.5 7 µA
tDHL HO off to LO on deadtime 12 22 35 ns
tDLH LO off to HO on deadtime 12 22 35 ns
VZCD-BOOST SENSE1 to SW ZCD threshold for boost 6 mV
VZCD-BUCK SW to PGND ZCD threshold for buck –5 mV
ICHG Charge pump current BIAS = 3.8 V 10 µA
THERMAL SHUTDOWN
TTSD-RISING Thermal shutdown threshold Temperature rising 175 °C
TTSD-HYS Thermal shutdown hysteresis 15 °C