SNVSA02A January   2016  – December 2016 LM5140-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Voltage Start-up Regulator
      2. 7.3.2  VCC Regulator
      3. 7.3.3  Oscillator
      4. 7.3.4  SYNIN and SYNOUT
      5. 7.3.5  Enable
      6. 7.3.6  Power Good
      7. 7.3.7  Output Voltage
      8. 7.3.8  Minimum Output Voltage Adjustment
      9. 7.3.9  Current Sense
      10. 7.3.10 DCR Current Sensing
      11. 7.3.11 Error Amplifier and PWM Comparator
      12. 7.3.12 Slope Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hiccup Mode Current Limiting
      2. 7.4.2 Standby Mode
      3. 7.4.3 Soft Start
      4. 7.4.4 Diode Emulation
      5. 7.4.5 High and low-side Drivers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Inductor Calculation
        2. 8.2.2.2  Current Sense Resistor
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Input Filter
        5. 8.2.2.5  EMI Filter Design
        6. 8.2.2.6  MOSFET Selection
        7. 8.2.2.7  Driver Slew Rate Control
        8. 8.2.2.8  Sub-Harmonic Oscillation
        9. 8.2.2.9  Control Loop
        10. 8.2.2.10 Error Amplifier
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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発注情報

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage VIN –0.3 70 V
SW1,SW2 to PGND –0.3 70 V
SW1, SW2 to PGND (20ns transient) –5 V
HB1 to SW1, HB2 to SW2 –0.3 6.5 V
HB1 to SW1, HB2 to SW2 (20ns transient) –5 V
HO1 to SW1, HOL1 to SW1, HO2 to SW2, HOL2 to SW2 –0.3 HB + 0.3 V
HO1 to SW1, HOL1 to SW1, HO2 to SW2, HOL2 to SW2 (20ns transient) –5 V
LO1, LOL1, LO2, LOL2 to PGND –0.3 VCC + 0.3 V
LO1, LOL1, LO2, LOL2 to PGND ( 20ns transient) –1.5 VCC + 0.3 V
OSC, SS1, SS2, COMP1, COMP2, RES, DEMB, ILSET –0.3 VDDA + 0.3 V
EN1, EN2 to PGND –0.3 70 V
VCC, VCCX, VDDA, PG1, PG2, FB1, FB2, SYNIN –0.3 6.5 V
VOUT1, VOUT2, CS1, CS2 –0.3 15.5 V
VOUT1 to CS1, VOUT2 to CS2 –0.3 0.3 V
PGND to AGND –0.3 0.3 V
Operating junction temperature(2) –40 150 ºC
Storage temperature, Tstg –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1)(2) ±2000 V
Charged-device model (CDM), per AEC Q100-011(3) All pins except 1, 10, 11, 20, 21, 30, 31, and 40 ±500
Pins 1, 10, 11, 20, 21, 30, 31, and 40 ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions(1)

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage VIN 3.8 65 V
SW1, SW2 to PGND –0.3 65 V
HB1 to SW1, HB2 to SW2 –0.3 5 5.25 V
HO1 to SW1, HOL1 to SW1, HO2 to SW2, HOL2 to SW2 –0.3 HB + 0.3 V
LO1, LOL1, LO2, LOL2 to PGND –0.3 5 5.25 V
FB1, FB2, PG1, PG2, SYNIN, OSC, SS1, SS2, RES, DEMB, VCCX, ILSET –0.3 5 V
EN1, EN2 to PGND –0.3 65 V
VCC, VDDA –0.3 5 5.25 V
VOUT1, VOUT2, CS1, CS2 1.5 5 15 V
VO Output voltage SYNOUT –0.3 5.25 V
PGND to AGND –0.3 0.3 V
TJ Operating junction temperature(2) –40 150 °C
(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

6.4 Thermal Information

THERMAL METRIC(1) LM5140-Q1 UNIT
RWG (VQFN)
40 PINS
RθJA Junction-to-ambient thermal resistance 34.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 22.8 °C/W
RθJB Junction-to-board thermal resistance 9.5 °C/W
ψJT Junction-to-top characterization parameter 1.3 °C/W
ψJB Junction-to-board characterization parameter 9.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

TJ = –40°C to 125°C, VIN = 12 V, VCCX = 5 V, VOUT1 = 3.3 V, VOUT2 = 5 V, EN1 = EN2 = 5 V, OSC = VDDA, SYNIN = 0 V, FSW = 2.2 MHz, no-load on the Drive Outputs (HO1, HOL1, LO2, LOL1, HO2, HOL2, LO2, and LOL2 outputs) (unless otherwise noted). (1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN SUPPLY VOLTAGE
I(SHUTDOWN) Shutdown mode current VIN 8 V- 18 V, EN1 = 0 V, EN2 = 0 V, VCCX = 0 V 9 12.5 µA
I(STANDBY) Standby current EN1 = 5 V, EN2 = 0 V, VOUT1, in regulation, no-load, not switching.
VIN 8 V - 18 V. DEMB = GND		 35 µA
Or EN1 = 0 V, EN2 = 5 V, VOUT2 in regulation, no-load, not switching, VOUT2 connected to VCCX,
DEMB = GND.		 42 µA
VCC REGULATOR
VCC(REG) VCC regulation voltage VIN = 6 V - 18 V, 0 - 150 mA,
VCCX = 0 V		 4.75 5 5.25 V
VCC(UVLO) VCC under voltage threshold VCC rising, VCCX = 0 V 3.25 3.4 3.55 V
VCC(HYST) VCC hysteresis voltage VCCX = 0 V 175 mV
ICC(LIM) VCC sourcing current limit VCCX = 0 V 170 250 mA
VDDA
VDDA(REG) Internal bias supply power VCCX = 0 V 4.75 5 5.25 V
VDDA(UVLO) VDDA undervoltage lockout VCC rising, VCCX = 0 V 3.1 3.2 3.3 V
VDDA(HYST) VDDA hysteresis voltage VCCX = 0 V 180 mV
R(VDDA) VDDA resistance VCCX = 0 V 50 Ω
VCCX
VCCX(ON) VCC(ON) threshold VCC rising 4.1 4.3 4.4 V
R(VCCX) VCCX resistance VCCX = 5 V 1 Ω
VCCX(HYST) VCCX hysteresis voltage 200 mV
OSCILLATOR SELECT THRESHOLDS
2.2-MHz Oscillator select threshold (OSC pin) 2.4 V
440-kHz Oscillator select threshold (OSC pin) 0.4 V
CURRENT LIMIT
V(CS1) Current limit threshold1 ILSET = VDDA, Measure from
CS to VOUT		 66 73 80 mV
V(CS2) Current limit threshold2 ILSET = GND, Measure from
CS to VOUT		 44 48 53 mV
Current sense delay to output 40 ns
Current sense amplifier gain 11.4 12 12.6 V/V
ICS(BIAS) Amplifier input bias 10 nA
75-mV current limit select threshold (ILSET) 2.4 V
75-mV current limit select threshold (ILSET) 0.4 V
RES
I(RES) RES current source 20 µA
V(RES) RES threshold 1.2 V
Timer hIccup mode fault 512 cycles
RDS(ON) RES pulldown 5 Ω
OUTPUT VOLTAGE REGULATION
3.3 V VIN = 3.8 V - 42 V 3.273 3.3 3.327 V
5 V VIN = 5.5 V - 42 V 4.95 5 5.05 V
8 V VIN = 8.5 V - 42 V 7.92 8 8.08 V
FEEDBACK
VOUT1 select threshold 3.3-V Output VDDA – 0.3 V
VOUT2 select threshold 5 V VDDA – 0.3 V
Regulated Feedback Voltage 1.19 1.2 1.21 V
FB(LOWRES) Resistance to ground on FB for FB=0 detection 500 Ω
FB(EXTRES) Thevenin equivalent resistance at FB for external regulation detection FB < 2 V 5 kΩ
TRANSCONDUCTANCE AMPLIFIER
Gm Gain Feedback to COMP 1010 1200 µS
FB Input Bias Current 15 nA
Transconductance Amplifier source current COMP = 1 V, FB = 1.0 V 100 µA
Transconductance Amplifier sink current COMP = 1 V, FB = 1.4 V 100 µA
POWER GOOD
PG(UV) PG1 and PG2 Under Voltage trip levels Falling with respect to the regulation voltage 90% 92% 94%
PG(OVP) PG1 and PG2 Over Voltage trip levels Rising with respect to the regulation voltage 108% 110% 112%
PG(HYST) Power Good hysteresis voltage 3.4%
PG(VOL) PG1 and PG2 Open Collector, Isink = 2 mA 0.4 V
PG(rdly) OV Filter Time VOUT rising 25 µs
PG(fdly) UV Filter Time VOUT falling 30 µs
HO GATE DRIVER
VOLH HO Low-state output voltage IHO = 100 mA 0.05 V
VOHH HO High-state output voltage IHO = -100 mA, VOHH = VHB - VHO 0.07 V
trHO HO rise time (10% to 90%) CLOAD = 2700 pf 4 ns
tfHO HO fall time (90% to 10%) CLOAD = 2700 pf 3 ns
IOHH HO peak source current VHO = 0 V, SW = 0 V, HB = 5 V, VCCX = 5 V 3.25 Apk
IOLH HO peak sink current VCCX = 5 V 4.25 Apk
V(BOOT) UVLO HO falling 2.5 V
Hysteresis 110 mV
I(BOOT) Quiescent current 3 µA
LO GATE DRIVER
VOLL LO Low-state Output Voltage ILO = 100 mA 0.05 V
VOHL LO High-state Output voltage ILO = -100 mA, VOHL = VCC - VLO 0.07 V
trLO LO rise time (10% to 90%) CLOAD = 2700 pf 4 ns
tfLO LO fall time (90% to 10%) CLOAD = 2700 pf 3 ns
IOHL LO peak source current VCCX = 5 V 3.25 Apk
IOLL LO peak sink current VCCX = 5 V 4.25 Apk
ADAPTIVE DEAD TIME CONTROL
V(GS-DET) VGS detection threshold VGS falling, no-load 2.5 V
tdly1 HO off to LO on dead time 20 ns
tdly2 LO off to HO on dead time 15 ns
DIODE EMULATION
VIL DEM input low threshold 0.4 V
VIH FPWM input high threshold 2.4 V
SW zero cross threshold –5 mV
ENABLE INPUTS EN1 AND EN2
VIL Enable input low threshold VCCX = 0 V 0.4 V
VIH Enable input high threshold VCCX = 0 V 2.4 V
Ilkg Leakage EN1, EN2 logic inputs only 1 µA
SYN INPUT
VIL SYNIN input low threshold 0.4 V
VIH SYNIN input high threshold 2.4 V
SYNIN input low frequency range 440 kHz 350 550 kHz
SYNIN input low frequency range 2.2 MHz 1800 2600 kHz
SYN OUTPUT
VOH SYN output high output voltage Source -16 mA, VDDA = 5 V 2.4 V
VOL SYN Output low level output voltage Sink 16 mA 0.4 V
Phase between HO1 and HO2 180 degrees
Duty Cycle 50%
SOFT-START
ISS Soft-start current 16 22 28 µA
RDS(ON) Soft-start pulldown resistance 3 Ω
THERMAL
TSD thermal shutdown 175 ºC
Thermal shutdown hysteresis 15 ºC
(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
(2) The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as follows: TJ = TA + (PD • RθJA) where RθJA (in °C/W) is the package thermal impedance provided in the Thermal Information section.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Oscillator frequency, 2.2 MHz OSC = VDDA, VIN = 8 V – 18 V 2060 2200 2340 kHz
Oscillator frequency, 440 kHz OSC = GND, VIN = 8 V – 18 V 410 440 470 kHz
ton Minimum on-time 45 ns
toff Minimum off-time 100 ns

6.7 Typical Characteristics

LM5140-Q1 D001_SNVSA02.gif
VIN 8-18 V EN1 = EN2 = 12 V 2.2 MHz
Figure 1. Efficiency vs VIN, FPWM
LM5140-Q1 D003_SNVSA02.gif
VIN 8-18 V EN1 = EN2 = 12 V
Figure 3. I(SHUTDOWN) vs Temperature
LM5140-Q1 D005_SNVSA02.gif
VIN 6-18V EN1 = EN2 = 12 V
Figure 5. VCC(REG) vs VIN
LM5140-Q1 D007_SNVSA02.gif
VCC Rising EN1 = EN2 = 12 V
Figure 7. VDDA(REG) vs Temperature
LM5140-Q1 D009_SNVSA02.gif
VIN = 12 V VCC Rising
Figure 9. VCCX(ON) vs Temperature
LM5140-Q1 D011_SNVSA02.gif
VIN = 12 V ILSET = GND
Figure 11. V(CS2) 48-mV Current Limit Threshold vs Temperature
LM5140-Q1 D013_SNVSA02.gif
VIN 12 V EN1 = 12 V EN2 = GND
Figure 13. 3.3-V Output Voltage Regulation
LM5140-Q1 D015_SNVSA02.gif
VIN 12 V OSC = VCC
Figure 15. 2.2-MHz Oscillator Frequency vs Temperature
LM5140-Q1 D017_SNVSA02.gif
VIN 18 V
Figure 17. ton Minimum vs Temperature
LM5140-Q1 D002_SNVSA02.gif
VIN 8-18 V EN1 = EN2 = 12 V 2.2 MHz
Figure 2. Efficiency vs VIN, DEMB
LM5140-Q1 D004_SNVSA02.gif
VIN 8-18 V EN1 = 12 V, EN2 = 0 V 2.2 MHz
Figure 4. I(STANDBY) vs VIN
LM5140-Q1 D006_SNVSA02.gif
VCC Rising EN1 = EN2 = 12 V
Figure 6. VCC(UVLO) vs Temperature
LM5140-Q1 D008_SNVSA02.gif
VCC Rising
Figure 8. VDDA(UVLO) vs Temperature
LM5140-Q1 D010_SNVSA02.gif
VIN = 12 V ILSET = VCC
Figure 10. V(CS1) 73-mV Current Limit Threshold vs Temperature
LM5140-Q1 D012_SNVSA02.gif
VCC Rising
Figure 12. Current Sense Amplifier Gain vs Temperature
LM5140-Q1 D014_SNVSA02.gif
VIN 5.5 V - 42 V EN1 = GND EN2 = 12 V
Figure 14. 5-V Output Voltage Regulation
LM5140-Q1 D016_SNVSA02.gif
VIN 12 V OSC = GND
Figure 16. 440-kHz Oscillator Frequency vs Temperature
LM5140-Q1 D018_SNVSA02.gif
VIN 3.8 V
Figure 18. toff Minimum vs Temperature