JAJSCD9D July   2016  – December 2017 LM5141-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Voltage Start-up Regulator
      2. 7.3.2  VCC Regulator
      3. 7.3.3  Oscillator
      4. 7.3.4  Synchronization
      5. 7.3.5  Frequency Dithering (Spread Spectrum)
      6. 7.3.6  Enable
      7. 7.3.7  Power Good
      8. 7.3.8  Output Voltage
        1. 7.3.8.1 Minimum Output Voltage Adjustment
      9. 7.3.9  Current Sense
      10. 7.3.10 DCR Current Sensing
      11. 7.3.11 Error Amplifier and PWM Comparator
      12. 7.3.12 Slope Compensation
      13. 7.3.13 Hiccup Mode Current Limiting
      14. 7.3.14 Standby Mode
      15. 7.3.15 Soft Start
      16. 7.3.16 Diode Emulation
      17. 7.3.17 High- and Low-Side Drivers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Inductor Calculation
        3. 8.2.2.3 Current Sense Resistor
        4. 8.2.2.4 Output Capacitor
        5. 8.2.2.5 Input Filter
          1. 8.2.2.5.1 EMI Filter Design
          2. 8.2.2.5.2 MOSFET Selection
          3. 8.2.2.5.3 Driver Slew-Rate Control
          4. 8.2.2.5.4 Frequency Dithering
        6. 8.2.2.6 Control Loop
          1. 8.2.2.6.1 Feedback Compensator
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Procedure
    2. 10.2 Layout Examples
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGE|24
サーマルパッド・メカニカル・データ
発注情報

8.2.2.2 Inductor Calculation

For peak current mode control, sub-harmonic oscillation occurs with a duty cycle greater than 50% and is characterized by alternating wide and narrow pulses at the SW pin. By adding a slope compensating ramp equal to at least one-half the inductor current down-slope, any tendency toward sub-harmonic oscillation is damped within one switching cycle. For design simplification, the LM5141-Q1 has an internal slope compensation ramp added to the current sense signal.

For the slope compensation ramp to dampen sub-harmonic oscillation, the inductor value should be calculated based on the following guidelines (Equation 15 assumes an inductor ripple current 30%):

Equation 15. LM5141-Q1 equation_14_snvsaj6.gif
  • Lower inductor values increase the peak-to-peak inductor current, which minimizes size and cost and improves transient response at the expense of reduced efficiency due to higher peak currents.
  • Higher inductance values decrease the peak-to-peak inductor current, which typically increases efficiency by reducing the RMS current but requires larger output capacitors to meet load-transient specifications.
Equation 16. LM5141-Q1 equation_15_snvsaj6.gif
LM5141-Q1 equation_15.1_snvsaj6.gif

A standard inductor value of 1.5 µH was selected

Equation 17. LM5141-Q1 equation_16_snvsaj6.gif
Equation 18. LM5141-Q1 equation_17_snvsaj6.gif

The peak-to-peak inductor current is:

Equation 19. LM5141-Q1 equation_18_snvsaj6.gif
Equation 20. LM5141-Q1 equation_19_snvsaj6.gif
Equation 21. LM5141-Q1 equation_20_snvsaj6.gif
Equation 22. LM5141-Q1 equation_21_snvsaj6.gif