JAJSJD3A June   2021  – June 2021 LM5146

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1. 6.1 Wettable Flanks
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Range (VIN)
      2. 8.3.2  Output Voltage Setpoint and Accuracy (FB)
      3. 8.3.3  High-Voltage Bias Supply Regulator (VCC)
      4. 8.3.4  Precision Enable (EN/UVLO)
      5. 8.3.5  Power Good Monitor (PGOOD)
      6. 8.3.6  Switching Frequency (RT, SYNCIN)
        1. 8.3.6.1 Frequency Adjust
        2. 8.3.6.2 Clock Synchronization
      7. 8.3.7  Configurable Soft Start (SS/TRK)
        1. 8.3.7.1 Tracking
      8. 8.3.8  Voltage-Mode Control (COMP)
      9. 8.3.9  Gate Drivers (LO, HO)
      10. 8.3.10 Current Sensing and Overcurrent Protection (ILIM)
      11. 8.3.11 OCP Duty Cycle Limiter
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
      4. 8.4.4 Diode Emulation Mode
      5. 8.4.5 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Design and Implementation
      2. 9.1.2 Power Train Components
        1. 9.1.2.1 Inductor
        2. 9.1.2.2 Output Capacitors
        3. 9.1.2.3 Input Capacitors
        4. 9.1.2.4 Power MOSFETs
      3. 9.1.3 Control Loop Compensation
      4. 9.1.4 EMI Filter Design
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – 12-A High-Efficiency Synchronous Buck DC/DC Regulator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Custom Design With WEBENCH® Tools
        4. 9.2.1.4 Custom Design With Excel Quickstart Tool
        5. 9.2.1.5 Application Curves
      2. 9.2.2 Design 2 – High Density, 12-V, 8-A Rail From 48-V Telecom Power
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Stage Layout
      2. 11.1.2 Gate Drive Layout
      3. 11.1.3 PWM Controller Layout
      4. 11.1.4 Thermal Design and Layout
      5. 11.1.5 Ground Plane Design
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
        1. 12.2.1.1 PCB Layout Resources
        2. 12.2.1.2 Thermal Design Resources
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.4 Precision Enable (EN/UVLO)

The EN/UVLO input supports adjustable input undervoltage lockout (UVLO) with hysteresis programmed by the resistor values for application specific power-up and power-down requirements. EN/UVLO connects to a comparator-based input referenced to a 1.2-V bandgap voltage. An external logic signal can be used to drive the EN/UVLO input to toggle the output ON and OFF and for system sequencing or protection. The simplest way to enable the operation of the LM5146 is to connect EN/UVLO directly to VIN. This allows self start-up of the LM5146 when VCC is within its valid operating range. However, many applications benefit from using a resistor divider RUV1 and RUV2 as shown in Figure 8-3 to establish a precision UVLO level.

Use Equation 1 and Equation 2 to calculate the UVLO resistors given the required input turn-on and turn-off voltages.

Equation 1. GUID-F6969E72-AAAD-4DA2-A113-C1EF49D566E1-low.gif
Equation 2. GUID-02726C2D-4C03-4D6B-B054-9F2DEDE6C30B-low.gif
Figure 8-3 Programmable Input Voltage UVLO Turn-on and Turn-off

The LM5146 enters a low IQ shutdown mode when EN/UVLO is pulled below approximately 0.4 V. The internal LDO regulator powers off and the internal bias supply rail collapses, shutting down the bias currents of the LM5146. The LM5146 operates in standby mode when the EN/UVLO voltage is between the hard shutdown and precision enable (standby) thresholds.