JAJSKS0C December   2020  – February 2023 LM5149-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1. 6.1 Wettable Flanks
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings 
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Active EMI Filter
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN)
      2. 8.3.2  High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA)
      3. 8.3.3  Precision Enable (EN)
      4. 8.3.4  Power-Good Monitor (PG)
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Active EMI Filter
      7. 8.3.7  Dual Random Spread Spectrum (DRSS)
      8. 8.3.8  Soft Start
      9. 8.3.9  Output Voltage Setpoint (FB)
      10. 8.3.10 Minimum Controllable On Time
      11. 8.3.11 Error Amplifier and PWM Comparator (FB, EXTCOMP)
      12. 8.3.12 Slope Compensation
      13. 8.3.13 Inductor Current Sense (ISNS+, VOUT)
        1. 8.3.13.1 Shunt Current Sensing
        2. 8.3.13.2 Inductor DCR Current Sensing
      14. 8.3.14 Hiccup Mode Current Limiting
      15. 8.3.15 High-Side and Low-Side Gate Drivers (HO, LO)
      16. 8.3.16 Output Configurations (CNFG)
      17. 8.3.17 Single-Output Dual-Phase Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
      2. 8.4.2 Pulse Frequency Modulation and Synchronization (PFM/SYNC)
      3. 8.4.3 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Power Train Components
        1. 9.1.1.1 Buck Inductor
        2. 9.1.1.2 Output Capacitors
        3. 9.1.1.3 Input Capacitors
        4. 9.1.1.4 Power MOSFETs
        5. 9.1.1.5 EMI Filter
        6. 9.1.1.6 Active EMI Filter
      2. 9.1.2 Error Amplifier and Compensation
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – High-Efficiency 2.1-MHz Synchronous Buck Regulator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2  Custom Design With Excel Quickstart Tool
          3. 9.2.1.2.3  Buck Inductor
          4. 9.2.1.2.4  Current-Sense Resistance
          5. 9.2.1.2.5  Output Capacitors
          6. 9.2.1.2.6  Input Capacitors
          7. 9.2.1.2.7  Frequency Set Resistor
          8. 9.2.1.2.8  Feedback Resistors
          9. 9.2.1.2.9  Compensation Components
          10. 9.2.1.2.10 Active EMI Components
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – High Efficiency 48-V to 12-V 400-kHz Synchronous Buck Regulator
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Design 3 – High Efficiency 440-kHz Synchronous Buck Regulator
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Design 4 – Dual-Phase 400-kHz 20-A Synchronous Buck Regulator
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Power Stage Layout
        2. 9.4.1.2 Gate-Drive Layout
        3. 9.4.1.3 PWM Controller Layout
        4. 9.4.1.4 Active EMI Layout
        5. 9.4.1.5 Thermal Design and Layout
        6. 9.4.1.6 Ground Plane Design
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
        1. 10.2.1.1 PCB Layout Resources
        2. 10.2.1.2 Thermal Design Resources
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.1.1.4 Power MOSFETs

The choice of power MOSFETs has significant impact on DC/DC regulator performance. A MOSFET with low on-state resistance, RDS(on), reduces conduction loss, whereas low parasitic capacitances enable faster transition times and reduced switching loss. Normally, the lower the RDS(on) of a MOSFET, the higher the gate charge and output charge (QG and QOSS, respectively), and vice versa. As a result, the product of RDS(on) and QG is commonly specified as a MOSFET figure-of-merit. Low thermal resistance of a given package ensures that the MOSFET power dissipation does not result in excessive MOSFET die temperature.

The main parameters affecting power MOSFET selection in a LM5149-Q1 application are as follows:

  • RDS(on) at VGS = 4.5 V
  • Drain-source voltage rating, BVDSS, typically 40 V, 60 V , or 80 V, depending on the maximum input voltage
  • Gate charge parameters at VGS = 4.5 V
  • Output charge, QOSS, at the relevant input voltage
  • Body diode reverse recovery charge, QRR
  • Gate threshold voltage, VGS(th), derived from the Miller plateau evident in the QG versus VGS plot in the MOSFET data sheet. With a Miller plateau voltage typically in the range of 2 V to 3 V, the 5-V gate drive amplitude of the LM5149-Q1 provides an adequately enhanced MOSFET when on and a margin against Cdv/dt shoot-through when off.

The MOSFET-related power losses for one channel are summarized by the equations presented in Table 9-1, where suffixes one and two represent high-side and low-side MOSFET parameters, respectively. While the influence of inductor ripple current is considered, second-order loss modes, such as those related to parasitic inductances and SW node ringing, are not included. Consult the LM5149-Q1 Quickstart Calculator.

Table 9-1 MOSFET Power Losses
POWER LOSS MODEHIGH-SIDE MOSFETLOW-SIDE MOSFET
MOSFET conduction(2)(3)GUID-229D3ECC-49F3-4A40-AF06-A48338C4138D-low.gifGUID-4689C670-52B6-4D12-9D60-CA4E205C6749-low.gif
MOSFET switchingGUID-F83F7A50-954C-4050-9516-19A66BDEAB9C-low.gifNegligible
MOSFET gate drive(1)GUID-0C16DC84-1232-47F2-BDDB-4C87C33D8CC3-low.gifGUID-4A2A451F-A771-4972-AA1C-98EA65A76CD8-low.gif
MOSFET output charge(4)GUID-7984FF70-5C8A-497D-89A8-8C786921601E-low.gif
Body diode
conduction		N/AGUID-4D571AA5-4C24-46E2-ABEB-81FFE85CB5DA-low.gif
Body diode
reverse recovery(5)		GUID-8347A1BC-6F08-458B-8B4D-B428C0C016B5-low.gif
(1) Gate drive loss is apportioned based on the internal gate resistance of the MOSFET, externally added series gate resistance and the relevant driver resistance of the LM5149-Q1.
(2) MOSFET RDS(on) has a positive temperature coefficient of approximately 4500 ppm/°C. The MOSFET junction temperature, TJ, and its rise over ambient temperature is dependent upon the device total power dissipation and its thermal impedance. When operating at or near minimum input voltage, make sure that the MOSFET RDS(on) is rated for the available gate drive voltage.
(3) D' = 1–D is the duty cycle complement.
(4) MOSFET output capacitances, Coss1 and Coss2, are highly non-linear with voltage. These capacitances are charged without losses by the inductor current at high-side MOSFET turnoff. During turn-on, however, a current flows from the input to charge the output capacitance of the low-side MOSFET. Eoss1, the energy of Coss1, is dissipated at turn-on, but this is offset by the stored energy Eoss2 on Coss2.
(5) MOSFET body diode reverse recovery charge, QRR, depends on many parameters, particularly forward current, current transition speed and temperature.

The high-side (control) MOSFET carries the inductor current during the PWM on time (or D interval) and typically incurs most of the switching losses. The high-side (control) MOSFET is therefore imperative to choose a high-side MOSFET that balances conduction and switching loss contributions. The total power dissipation in the high-side MOSFET is the sum of the losses due to conduction, switching (voltage-current overlap), output charge, and typically two-thirds of the net loss attributed to body diode reverse recovery.

The low-side (synchronous) MOSFET carries the inductor current when the high-side MOSFET is off (or during the 1–D interval). The low-side MOSFET switching loss is negligible as it is switched at zero voltage – current just communicates from the channel to the body diode or vice versa during the transition deadtimes. LM5149-Q1, with its adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such losses scale directly with switching frequency.

In high step-down ratio applications, the low-side MOSFET carries the current for a large portion of the switching period. Therefore, to attain high efficiency, optimizing the low-side MOSFET for low RDS(on) is critical. In cases where the conduction loss is too high or the target RDS(on) is lower than available in a single MOSFET, connect two low-side MOSFETs in parallel. The total power dissipation of the low-side MOSFET is the sum of the losses due to channel conduction, body diode conduction, and typically one-third of the net loss attributed to body diode reverse recovery. The LM5149-Q1 is well suited to drive TI's portfolio of NexFET™ power MOSFET.