JAJSL35 January   2021 LM5156 , LM51561

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Line Undervoltage Lockout (UVLO/SYNC/EN Pin)
      2. 9.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 9.3.3  Soft Start (SS Pin)
      4. 9.3.4  Switching Frequency (RT Pin)
      5. 9.3.5  Dual Random Spread Spectrum (DRSS)
      6. 9.3.6  Clock Synchronization (UVLO/SYNC/EN Pin)
      7. 9.3.7  Current Sense and Slope Compensation (CS Pin)
      8. 9.3.8  Current Limit and Minimum On-time (CS Pin)
      9. 9.3.9  Feedback and Error Amplifier (FB, COMP Pin)
      10. 9.3.10 Power-Good Indicator (PGOOD pin)
      11. 9.3.11 Hiccup Mode Overload Protection (LM51561 Only)
      12. 9.3.12 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
      13. 9.3.13 MOSFET Driver (GATE Pin)
      14. 9.3.14 Overvoltage Protection (OVP)
      15. 9.3.15 Thermal Shutdown (TSD)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Run Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Custom Design With WEBENCH® Tools
        2. 10.2.2.2 Recommended Components
        3. 10.2.2.3 Inductor Selection (LM)
        4. 10.2.2.4 Output Capacitor (COUT)
        5. 10.2.2.5 Input Capacitor
        6. 10.2.2.6 MOSFET Selection
        7. 10.2.2.7 Diode Selection
        8. 10.2.2.8 Efficiency Estimation
      3. 10.2.3 Application Curve
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Development Support
        1. 13.1.2.1 Custom Design With WEBENCH® Tools
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = -40°C to 125°C. Unless otherwise stated, VBIAS = 12 V, RT = 9.09 kΩ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
ISHUTDOWN(BIAS) BIAS shutdown current VBIAS = 12 V, VUVLO = 0 V 2.6 5 uA
IOPERATING(BIAS) BIAS operating current VBIAS = 12 V, VUVLO = 2.0 V, VFB = VREF, RT = 220 kΩ 490 550 uA
VCC REGULATOR
VVCC-REG VCC regulation VBIAS = 8 V, No load 6.5 6.85 7 V
VCC regulation VBIAS = 8 V, IVCC = 35 mA 6.5 V
VVCC-UVLO(RISING) VCC UVLO threshold VCC rising 2.75 2.85 2.95 V
VCC UVLO hysteresis VCC falling 0.063 V
IVCC-CL VCC sourcing current limit VBIAS = 10 V, VVCC = 0 V 35 110 mA
ENABLE
VEN(RISING) Enable threshold EN rising 0.4 0.52 0.7 V
VEN(FALLING) Enable threshold EN falling 0.33 0.49 0.63 V
VEN(HYS) Enable hysteresis EN falling 0.03 V
UVLO/SYNC
VUVLO(RISING) UVLO / SYNC threshold UVLO rising 1.425 1.5 1.575 V
VUVLO(FALLING) UVLO / SYNC threshold UVLO falling 1.370 1.45 1.520 V
VUVLO(HYS) UVLO / SYNC threshold hysteresis UVLO falling 0.05 V
IUVLO UVLO hysteresis current VUVLO = 1.6 V 4 5 6 uA
SPREAD SPECTRUM
VDITHOFF(RISING) Clock dithering threshold DITHOFF rising, VBIAS = 4 V 1.1 1.7 2.1 V
VDITHOFF(FALLING) Clock dithering threshold DITHOFF falling, VBIAS = 4 V 0.6 1.2 1.8 V
VDITHOFF(HYS) Clock dithering threshold hysteresis DITHOFF falling, VBIAS = 4 V 0.5 V
SS
ISS Soft-start current 9 10 11 uA
SS pull-down switch RDSON 55 Ω
PULSE WIDTH MODULATION
fsw1 Switching frequency RT = 220 kΩ, VBIAS = 4 V 85 100 115 kHz
fsw2 Switching frequency RT = 9.09 kΩ, VBIAS = 4 V 1980 2200 2420 kHz
tON(MIN) Minimum on-time RT = 9.09 kΩ 50 ns
DMAX1 Maximum duty cycle limit RT = 9.09 kΩ, VBIAS = 4 V 80 85 90 %
DMAX2 Maximum duty cycle limit RT = 220 kΩ, VBIAS = 4 V 90 93 96 %
CURRENT SENSE
ISLOPE Peak slope compensation current RT = 220 kΩ 22.5 30 37.5 uA
VCLTH Current Limit threshold (CS-GND) 93 100 107 mV
HICCUP MODE PROTECTION (LM51561)
Hiccup enable cycles 64 Cycles
Hiccup timer reset cycles 8 Cycles
ERROR AMPLIFIER
VREF FB reference LM5156, LM51561 0.99 1 1.01 V
Gm Transconductance 2 mA/V
COMP sourcing current VCOMP = 1.2 V 180 uA
COMP clamp voltage COMP rising (VUVLO = 2.0 V) 2.5 2.8 V
COMP clamp voltage COMP falling 1 1.1 V
OVP
VOVTH Over-voltage threshold FB rising (referece to VREF) 107 110 113 %
Over-voltage threshold FB falling (referece to VREF) 105 %
PGOOD
PGOOD pulldown switch RDSON 1 mA sinking 90 Ω
VUVTH Under-voltage threshold FB falling (referece to VREF) 87 90 93 %
Under-voltage threshold FB rising (referece to VREF) 95 %
MOSFET DRIVER
High-state voltage drop 100 mA sinking 0.25 V
Low-state voltage drop 100 mA sourcing 0.15 V
THERMAL SHUTDOWN
TTSD Thermal shutdown threshold Temperature rising 175 °C
Thermal shutdown hysteresis 15 °C