JAJSMQ7A August   2021  – October 2021 LM5158-Q1 , LM51581-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Line Undervoltage Lockout (EN/UVLO/SYNC Pin)
      2. 9.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 9.3.3  Soft Start (SS Pin)
      4. 9.3.4  Switching Frequency (RT Pin)
      5. 9.3.5  Dual Random Spread Spectrum – DRSS (MODE Pin)
      6. 9.3.6  Clock Synchronization (EN/UVLO/SYNC Pin)
      7. 9.3.7  Current Sense and Slope Compensation
      8. 9.3.8  Current Limit and Minimum On Time
      9. 9.3.9  Feedback and Error Amplifier (FB, COMP Pin)
      10. 9.3.10 Power-Good Indicator (PGOOD Pin)
      11. 9.3.11 Hiccup Mode Overload Protection (MODE Pin)
      12. 9.3.12 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
      13. 9.3.13 Internal MOSFET (SW Pin)
      14. 9.3.14 Overvoltage Protection (OVP)
      15. 9.3.15 Thermal Shutdown (TSD)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Run Mode
        1. 9.4.3.1 Spread Spectrum Enabled
        2. 9.4.3.2 Hiccup Mode Protection Enabled
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Boost Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Custom Design With WEBENCH® Tools
        2. 10.2.2.2 Recommended Components
        3. 10.2.2.3 Inductor Selection (LM)
        4. 10.2.2.4 Output Capacitor (COUT)
        5. 10.2.2.5 Input Capacitor
        6. 10.2.2.6 Diode Selection
      3. 10.2.3 Application Curve
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Development Support
        1. 13.1.2.1 Custom Design With WEBENCH® Tools
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.10 Power-Good Indicator (PGOOD Pin)

The device has a power-good indicator (PGOOD) to simplify sequencing and supervision. The PGOOD switches to a high impedance open-drain state when the FB pin voltage is greater than the feedback undervoltage threshold (VUVTH), the VCC is greater than the VCC UVLO threshold and the UVLO/EN is greater than the EN threshold. A 25-μs deglitch filter prevents any false pulldown of the PGOOD due to transients. The recommended minimum pullup resistor value is 10 kΩ.

Due to the internal diode path from the PGOOD pin to the BIAS pin, the PGOOD pin voltage cannot be greater than VBIAS + 0.3 V.