JAJSGD4C July   2015  – October 2018 LM5160-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的な同期整流降圧アプリケーション回路
      2.      代表的なFly-Buckアプリケーション回路
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Control Circuit
      2. 8.3.2  VCC Regulator
      3. 8.3.3  Regulation Comparator
      4. 8.3.4  Soft Start
      5. 8.3.5  Error Amplifier
      6. 8.3.6  On-Time Generator
      7. 8.3.7  Current Limit
      8. 8.3.8  N-Channel Buck Switch and Driver
      9. 8.3.9  Synchronous Rectifier
      10. 8.3.10 Enable / Undervoltage Lockout (EN/UVLO)
      11. 8.3.11 Thermal Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forced Pulse Width Modulation (FPWM) Mode
      2. 8.4.2 Undervoltage Detector
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Ripple Configuration
    2. 9.2 Typical Applications
      1. 9.2.1 LM5160-Q1 Synchronous Buck (10-V to 60-V Input, 5-V Output, 1.5-A Load)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2  Feedback Resistor Divider - RFB1, RFB2
          3. 9.2.1.2.3  Switching Frequency - RON
          4. 9.2.1.2.4  Inductor - L
          5. 9.2.1.2.5  Output Capacitor - COUT
          6. 9.2.1.2.6  Series Ripple Resistor - RESR
          7. 9.2.1.2.7  VCC and Bootstrap Capacitors - CVCC, CBST
          8. 9.2.1.2.8  Input Capacitor - CIN
          9. 9.2.1.2.9  Soft-Start Capacitor - CSS
          10. 9.2.1.2.10 EN/UVLO Resistors - RUV1, RUV2
        3. 9.2.1.3 Application Curves
      2. 9.2.2 LM5160-Q1 Isolated Fly-Buck (18-V to 32-V Input, 12-V, 4.5-W Isolated Output)
        1. 9.2.2.1 LM5160-Q1 Fly-Buck Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Selection of VOUT1 and Turns Ratio
          2. 9.2.2.2.2 Secondary Rectifier Diode
          3. 9.2.2.2.3 External Ripple Circuit
          4. 9.2.2.2.4 Output Capacitor - COUT2
        3. 9.2.2.3 Application Curves
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
        1. 12.1.2.1 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 125°C. Unless otherwise stated, VIN = 24 V.(1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
ISD Input shutdown current VIN = 24 V, VEN/UVLO = 0 V 50 90.7 µA
IOP Input operating current VIN = 24 V, VFB = 3 V, non-switching 2.3 2.84 mA
VCC SUPPLY
VCC Bias regulator output VIN = 24 V, ICC = 20 mA 6.47 7.5 8.52 V
VCC Bias regulator current limit VIN = 24 V 30 mA
VCC(UV) VCC undervoltage threshold VVCC rising 3.98 4.1 V
VCC(HYS) VCC undervoltage hysteresis VVCC falling 185 mV
VCC(LDO) VIN – VCC dropout voltage VIN = 4.5 V, IVCC = 20 mA 165 260 mV
HIGH-SIDE FET
RDS(ON) High-side on-state resistance VBST – VSW = 7 V, ISW = 1 A 0.29 Ω
BST(UV) Bootstrap gate drive UV VBST – VSW rising 2.93 3.6 V
BST(HYS) Gate drive UV hysteresis VBST – VSW falling 200 mV
LOW-SIDE FET
RDS(ON) Low-side on-state resistance ISW = 1 A 0.13 Ω
HIGH-SIDE CURRENT LIMIT
ILIM(HS) High-side current limit threshold 2.125 2.5 2.875 A
TRES Current limit response time ILIM(HS) threshold detect to FET turnoff 100 ns
TOFF1 Current limit forced off-time VFB = 0 V, VIN = 65 V 16 29 39.8 µs
TOFF2 Current limit forced off-time VFB = 1 V, VIN = 24 V 2.18 3.5 5.12 µs
LOW-SIDE CURRENT LIMIT
ISOURCE(LS) Sourcing current limit 1.9 2.5 3 A
ISINK(LS) Sinking current limit 5.4 A
DIODE EMULATION
VFPWM(LOW) FPWM input logic low VIN = 24 V 1 V
VFPWM(HIGH) FPWM input logic high VIN = 24 V 3 V
IZX Zero cross detect current FPWM = AGND (diode emulation) 0 mA
REGULATION COMPARATOR
VREF FB regulation level VIN = 24 V 1.975 1.995 2.015 V
I(Bias) FB input bias current VIN = 24 V 100 nA
ERROR CORRECTION AMPLIFIER and SOFT START
GM Error amp transconductance VFB = VREF ± 10 mV 105 µA/V
IEA(Source) Error amp source current VFB = 1 V, VSS = 1 V 7.62 10.2 12.51 µA
IEA(Sink) Error amp sink current VFB = 5 V, VSS = 2.25 V 7.46 10 12.2 µA
V(SS-FB) VSS – VFB clamp voltage VFB = 1.75 V, CSS= 1 nF 135 mV
ISS Soft-start charging current VSS = 0.5 V 7.63 10.2 12.5 µA
ENABLE/UVLO
VUVLO(TH) UVLO threshold VEN/UVLO rising 1.213 1.24 1.277 V
IUVLO(HYS) UVLO hysteresis current VEN/UVLO = 1.4 V 15 20 25 µA
VSD(TH) Shutdown mode threshold VEN/UVLO falling 0.28 0.35 V
VSD(HYS) Shutdown threshold hysteresis VEN/UVLO rising 47 mV
THERMAL SHUTDOWN
TSD Thermal shutdown threshold 175 °C
TSD(HYS) Thermal shutdown hysteresis 20 °C
(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
(2) The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as follows: TJ = TA + (PD • RθJA) where RθJA (in °C/W) is the package thermal impedance provided in Thermal Information.