7.3.1 Control Circuit

The LM5161-Q1 step-down switching regulator employs a control principle based on a comparator and a one-shot ON-timer, with the output voltage feedback (FB) compared to the voltage at the Soft-Start (SS) pin (V_SS). If the FB voltage is below V_SS, the internal buck switch is turned on for a time period determined by the input voltage and one-shot programming resistor (R_ON). Following the ON-time, the buck switch must remain off for the minimum OFF-time forced by the minimum OFF-time one-shot. The buck switch remains off until the FB voltage falls below V_SS again, when it turns on for another ON-time one-shot period.

During a rapid start-up or when the load current increases suddenly, the regulator operates with minimum off-time per cycle. When regulating the output in steady state operation, the off-time automatically adjusts to produce the SW pin duty cycle required for output voltage regulation.

When in regulation, the LM5161-Q1 operates in continuous conduction mode at heavy load currents. If the FPWM pin is connected to ground or left floating, the regulator operates in discontinuous conduction mode at light load with the synchronous rectifier FET emulating a diode. With sufficient load, the LM5161-Q1 operates in continuous conduction mode with the inductor current never reaching zero during the OFF-time of the high-side FET. In this mode the operating frequency remains relatively constant with load and line variations. The minimum load current for continuous conduction mode is one-half the inductor’s ripple current amplitude. The operating frequency (in Hz) is programmed by the RON pin resistor and can be calculated from Equation 1 with R_ON expressed in ohms.

Equation 1.

In discontinuous conduction mode, current through the inductor ramps up from zero to a peak value during the ON-time, then ramps back to zero before the end of the OFF-time. The next ON-time period starts when the voltage at FB falls below V_SS. When the inductor current is zero during the high side FET off-time, the load current is supplied by the output capacitor. In this mode, the operating switching frequency is lower than the continuous conduction mode switching frequency and the frequency varies with load. The discontinuous conduction mode maintains higher conversion efficiency at light loads since the switching losses decrease with the decrease in load and frequency.

The output voltage is set by two external resistors ( R_FB1, R_FB2). The regulated output voltage is calculated from Equation 2, where V_REF = 2 V (typical) is the feedback reference voltage.

Equation 2.

7.3.2 VCC Regulator

The LM5161-Q1 contains an internal high voltage linear regulator with a nominal output voltage of 7.3 V (typical). The VCC regulator is internally current limited to 30 mA (minimum). This regulator supplies power to internal circuit blocks including the synchronous FET gate driver and the logic circuits. When the voltage on the VCC pin reaches the undervoltage lockout (V_CC(UV)) threshold of 3.98 V (typical), the IC is enabled. An external capacitor at the VCC pin stabilizes the regulator and supplies transient VCC current to the gate drivers. An internal diode connected from VCC to the BST pin replenishes the charge in the high-side gate drive bootstrap capacitor when the SW pin is low.

In high input voltage applications, the power dissipated in the regulator is significant and can limit the efficiency and maximum achievable output power. The LM5161-Q1 allows the internal VCC regulator power loss to be reduced by supplying the VCC voltage via a diode from an external voltage source regulated between 9 V and 13 V. The external VCC bias can be supplied from the LM5161-Q1 converter output rail if the regulation voltage is within this range. When the VCC pin of the LM5161-Q1 is raised above the regulation voltage (7.3 V typical), the internal regulator is disabled and the power dissipation in the IC is reduced.

7.3.3 Regulation Comparator

The feedback voltage at the FB pin is compared to the SS pin voltage V_SS. In normal operation when the output voltage is in regulation, an ON-time period is initiated when the voltage at FB pin falls below V_SS. The high-side buck switch stays on for the ON-time one-shot period causing the FB voltage to rise. After the on-time period expires, the high-side switch will remain off until the FB voltage falls below V_SS. During start-up, the FB voltage is below V_SS at the end of each on-time period and the high-side switch turns on again after the minimum forced off-time of 170 ns (typical). When the output is shorted to ground (FB = 0 V), the high side peak current limit is triggered, the high-side FET is turned off, and remains off for a period determined by the current limit OFF-time one-shot. See the Current Limit section for additional information.

7.3.4 Soft-Start

The soft-start feature of the LM5161-Q1 allows the converter to gradually reach a steady-state operating point, thereby reducing start-up stresses and current surges. When the EN/UVLO pin is above the EN/UVLO standby threshold V_UVLO(TH) = 1.24 V (typical) and VCC exceeds the VCC undervoltage V_CC(UV) = 3.98 V (typical) threshold, an internal 10-µA current source charges the external capacitor at the SS pin (C_SS) from 0 V to 2 V. The voltage at the SS pin is connected to the noninverting input of the internal FB comparator. The soft-start interval ends when the SS capacitor is charged to the 2 V reference level. The ramping voltage at the SS pin produces a controlled, monotonic output voltage start-up. A minimum 1-nF soft-start capacitor must be used in all applications.

7.3.5 Error Transconductance (G_M) Amplifier

The LM5161-Q1 provides a trans-conductance (G_M) error amplifier that minimizes the difference between the reference voltage (V_REF) and the average feedback (FB) voltage. This amplifier reduces the load and line regulation errors that are common in constant-on-time regulators. The soft-start capacitor (C_SS) provides compensation for this error correction loop. The soft-start capacitor should be greater than 1 nF to ensure stability.

7.3.6 On-Time Generator

The ON-time of the LM5161-Q1 high-side FET is determined by the R_ON resistor and is inversely proportional to the input voltage (V_IN). The inverse relationship with V_IN results in a nearly constant frequency as V_IN is varied. The ON-time can be calculated from Equation 3 with R_ON expressed in ohms.

Equation 3.

To set a specific continuous conduction mode switching frequency (F_SW expressed in Hz), the R_ON resistor is determined from Equation 4:

Equation 4.

R_ON must be selected for a minimum on-time (at maximum V_IN) greater than 150 ns for proper operation. This minimum ON-time requirement limits the maximum switching frequency of applications with relatively high V_IN and low V_OUT.

7.3.7 Current Limit

The LM5161-Q1 provides an intelligent current limit OFF-timer that adjusts the OFF-time to reduce foldback of the current limit. If the peak value of the current in the buck switch exceeds 1.6 A (typical) the present ON-time period is immediately terminated, and a non-resettable OFF-timer is initiated. The length of the OFF-time is controlled by the FB voltage and the input voltage V_IN. As an example, when V_FB = 0.1-V and V_IN = 72-V, the OFF-time is set to 13 μs (typical). This condition would occur if the output is shorted or during the initial phase of start-up. In cases of output overload where the FB voltage is greater than zero volts (a soft short), the current limit OFF-time is reduced. Reducing the OFF-time during less severe overloads reduces the current limit foldback, overload recovery time, and start-up time. The current limit off-time, T_OFF(CL) is calculated from Equation 5:

Equation 5.

7.3.8 N-Channel Buck Switch and Driver

The LM5161-Q1 integrates an N-channel buck switch and associated floating high-side gate driver. The gate driver circuit works in conjunction with an external bootstrap capacitor and an internal high voltage bootstrap diode. A 10-nF or larger ceramic capacitor connected between the BST pin and the SW pin provides the voltage to the high-side driver during the buck switch ON-time. During the OFF-time, the SW node is pulled down to approximately 0 V and the bootstrap capacitor charges from VCC through the internal bootstrap diode. The minimum OFF-time of 170 ns (typical) provides a minimum time each cycle to recharge the bootstrap capacitor.

7.3.9 Synchronous Rectifier

The LM5161-Q1 provides an internal low-side synchronous rectifier N-channel FET. This low-side FET provides a low resistance path for the inductor current when the high-side FET is turned off.

With the FPWM pin connected to ground or left floating, the LM5161-Q1 synchronous rectifier operates in diode emulation mode. Diode emulation enables the pulse-skipping during light load conditions. This leads to a reduction in the average switching frequency at light loads. Switching losses and FET gate driver losses, both of which are proportional to switching frequency, are significantly reduced and efficiency is improved. This pulse-skipping mode also reduces the circulating inductor currents and losses associated with a continuous conduction mode (CCM). When the FPWM pin is grounded or left floating, an internal ripple injection circuit is enabled. With the internal ripple injection enabled, the typical external feedback ripple injection circuit is no longer required. This feature reduces the component count in the buck applications. For more details see Forced Pulse Width Modulation (FPWM) Mode.

When the FPWM pin is pulled high, diode emulation is disabled. The inductor current can flow in either direction through the low-side FET resulting in CCM operation with nearly constant switching frequency. A negative sink current limit circuit limits the current that can flow into the SW pin and through the low-side FET to ground. In a buck regulator application, large negative current will only flow from V_OUT to the SW pin if V_OUT is lifted above the output regulation set-point.

7.3.10 Enable / Undervoltage Lockout (EN/UVLO)

The LM5161-Q1 contains a dual level undervoltage lockout (EN/UVLO) circuit. When the EN/UVLO pin voltage is below 0.35 V (typical), the regulator is in a low current shutdown mode. When the EN/UVLO pin voltage is greater than 0.35 V (typical) but less than 1.24 V (typical), the regulator is in standby mode. In standby mode, the VCC bias regulator is active but converter switching remains disabled. When the voltage at the VCC pin exceeds the VCC rising threshold V_CC(UV) = 3.98 V (typical) and the EN/UVLO pin voltage is greater than 1.24 V, normal switching operation begins. An external resistor voltage divider from VIN to GND can be used to set the minimum operating voltage of the regulator.

EN/UVLO hysteresis is accomplished with an internal 20-μA (typical) current source (I_UVLO(HYS)) that is switched on or off into the impedance of the EN/UVLO pin resistor divider. When the EN/UVLO threshold is exceeded, the current source is activated to effectively raise the voltage at the EN/UVLO pin. The hysteresis is equal to the value of this current times the upper resistance of the resistor divider, (R_UV2) (See Functional Block Diagram).

7.3.11 Thermal Protection

The LM5161-Q1 must be operated such that the junction temperature does not exceed 150°C during normal operation. An internal thermal shutdown circuit is provided to protect the LM5161-Q1 in the event of a higher than normal junction temperature. When activated, typically at 175°C, the controller is forced into a low-power reset state, disabling the high side buck switch and the VCC regulator. This feature prevents catastrophic failures due to device overheating. When the junction temperature falls below 155°C (typical hysteresis = 20°C), the VCC regulator is enabled, and operation resumes.

7.3.12 Ripple Configuration

LM5161-Q1 uses a Constant-On-Time (COT) control scheme, in which the ON-time is terminated by a one-shot, and the OFF-time is terminated by the feedback voltage (V_FB) falling below the reference voltage. Therefore, for stable operation, the feedback voltage must decrease monotonically and in phase with the inductor current during the OFF-time. Furthermore, this change in feedback voltage (V_FB) during OFF-time must be large enough to dominate any noise present at the feedback node.

Table 1 presents three different methods for generating appropriate voltage ripple at the feedback node. Type 1 and Type 2 ripple circuits couple the ripple from the output of the converter to the feedback node (FB). The output voltage ripple has two components:

1. Capacitive ripple caused by the inductor current ripple charging or discharging the output capacitor.
2. Resistive ripple caused by the inductor current ripple flowing through the ESR of the output capacitor and R3.

The capacitive ripple is out-of-phase with the inductor current. As a result, the capacitive ripple does not decrease monotonically during the OFF-time. The resistive ripple is in phase with the inductor current and decreases monotonically during the OFF-time. The resistive ripple must exceed the capacitive ripple at output (V_OUT) for stable operation. If this condition is not satisfied unstable switching behavior is observed in COT converters, with multiple ON-time bursts in close succession followed by a long OFF-time.

Type 3 ripple method uses a ripple injection circuit with R_A, C_A and the switch node (SW) voltage to generate a triangular ramp. This triangular ramp is then AC-coupled into the feedback node (FB) using the capacitor C_B. Since this circuit does not use the output voltage ripple, it is suited for applications where low output voltage ripple is imperative. See application note Controlling Output Ripple and Achieving ESR Independence in Constant On-Time (COT) Regulator Designs (SNVA166) for more details for each ripple generation method.

Table 1. Ripple Configuration

TYPE 1	TYPE 2	TYPE 3
Lowest Cost	Reduced Ripple	Minimum Ripple
Equation 6.	Equation 7.	Equation 8.

7.4.1 Forced Pulse Width Modulation (FPWM) Mode

The Synchronous Rectifier section gives a brief introduction to the LM5161-Q1 diode emulation feature. The FPWM pin allows the power supply designer to select either CCM or DCM mode of operation at light loads. When the FPWM pin is connected to ground or left floating (FPWM = 0), a pulse-skipping mode and the zero-cross current detector circuit is enabled. The zero-cross detector turns off the low-side FET when the inductor current falls close to zero (I_ZX, see Electrical Characteristics). This feature allows the LM5161-Q1 regulator to operate in DCM mode at light loads. In the DCM state, the switching frequency decreases with lighter loads.

When the FPWM pin is left open or shorted to ground, the user can take the advantage of the internal ripple injection circuit, enabled in this mode, for a typical Buck application circuit. This feature is applicable over the entire load and input voltage ranges. It eliminates the need for an external feedback ripple injection circuit.

For wide VIN applications where VIN > 72 V, an external VCC supply is commonly used to minimize the power dissipation in the IC. In such applications at T_J >125°C, it is recommended to add a BST resistor (> 3Ω) in series with the BST capacitor, in order to protect the internal VCC-BST diode during a full load transient operation. The addition of the external resistor will reduce the fast (dv/dt) of the switch node that can impact the normal IC operation.

If the FPWM pin is pulled high, the LM5161-Q1 will operate in CCM mode regardless of the load conditions. The CCM operation reduces efficiency at light load but improves the output transient response to step load changes and provides nearly constant switching frequency. Moreover, the Fly-Buck topology always requires the continuous conduction mode during its operation.

The internal ripple injection circuit is disabled in the CCM mode. An external ripple injection circuit or an additional ESR resistor in series with the output capacitor is required to generate the optimal ripple at the FB node. Also, there is no need to add any BST resistor in series with the BST capacitor in either forced CCM Buck or Fly-Buck application.

7.4.2 Undervoltage Detector

The following table summarizes the dual threshold levels of the undervoltage lockout (EN/UVLO) circuit explained in Enable / Undervoltage Lockout (EN/UVLO).

If an EN/UVLO setpoint is not required, the EN/UVLO pin can be driven by a logic signal as an enable input or connected directly to the VIN pin. If the EN/UVLO is directly connected to the VIN pin, the regulator will begin switching when the V_CC UVLO is satisfied.