JAJSIE2A december   2019  – april 2023 LM5163H-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Control Architecture
      2. 7.3.2  Internal VCC Regulator and Bootstrap Capacitor
      3. 7.3.3  Regulation Comparator
      4. 7.3.4  Internal Soft Start
      5. 7.3.5  On-Time Generator
      6. 7.3.6  Current Limit
      7. 7.3.7  N-Channel Buck Switch and Driver
      8. 7.3.8  Synchronous Rectifier
      9. 7.3.9  Enable/Undervoltage Lockout (EN/UVLO)
      10. 7.3.10 Power Good (PGOOD)
      11. 7.3.11 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 Sleep Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 High Temperature Specifications
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Switching Frequency (RRON)
        3. 8.2.2.3 Buck Inductor (LO)
        4. 8.2.2.4 Output Capacitor (COUT)
        5. 8.2.2.5 Input Capacitor (CIN)
        6. 8.2.2.6 Type 3 Ripple Network
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Compact PCB Layout for EMI Reduction
        2. 8.4.1.2 Feedback Resistors
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design with WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the full –40°C to 165°C junction temperature range unless otherwise indicated. VIN = 24 V and VEN/UVLO = 2 V unless otherwise stated.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLY CURRENT
IQ-SHUTDOWNVIN shutdown currentVEN = 0 V3µA
IQ-SLEEP1VIN sleep currentVEN = 2.5 V, VFB = 1.5 V10.5µA
IQ-ACTIVEVIN active currentVEN = 2.5 V600µA
EN/UVLO
VSD-RISINGShutdown thresholdVEN/UVLO rising1.1V
VSD-FALLINGShutdown thresholdVEN/UVLO falling0.45V
VEN-RISINGEnable threshold risingVEN/UVLO rising1.451.51.55V
VEN-FALLINGEnable threshold fallingVEN/UVLO falling1.351.41.44V
FEEDBACK
VREFFB regulation voltageVFB falling1.1811.21.218V
TIMING
tON1On-time1VVIN = 6 V, RRON = 75 kΩ5000ns
tON2On-time2VVIN = 6 V, RRON = 25 kΩ1650ns
tON3On-time3VVIN = 12 V, RRON = 75 kΩ2550ns
tON4On-time4VVIN = 12 V, RRON = 25 kΩ830ns
PGOOD
VPG-UTHFB upper threshold for PGOOD high to lowVFB rising1.1051.141.175V
VPG-LTHFB lower threshold for PGOOD high to lowVFB falling1.0551.081.1V
VPG-HYSPGOOD upper and lower threshold hysteresisVFB falling60mV
RPGPGOOD pulldown resistanceVFB = 1 V30Ω
BOOTSTRAP
VBST-UVGate drive UVLOVBST rising2.73.4V
POWER SWITCHES
RDSON-HSHigh-side MOSFET RDSONISW = –100 mA0.725Ω
RDSON-LSLow-side MOSFET RDSONISW = 100 mA0.33Ω
SOFT START
tSSInternal soft-start time1.7534.75ms
CURRENT LIMIT
IPEAK1Peak current limit threshold (HS)0.630.750.87A
IPEAK2Peak current limit threshold (LS)0.630.750.87A
IDELTA-ILIMMin of (IPEAK1 or IPEAK2) minus IVALLEY100mA
IVALLEYValley current limit threshold0.50.60.72A
THERMAL SHUTDOWN
TSDThermal shutdown thresholdTJ rising175°C
TSD-HYSThermal shutdown hysteresis10°C