JAJSIE2A
december 2019 – april 2023
LM5163H-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Control Architecture
7.3.2
Internal VCC Regulator and Bootstrap Capacitor
7.3.3
Regulation Comparator
7.3.4
Internal Soft Start
7.3.5
On-Time Generator
7.3.6
Current Limit
7.3.7
N-Channel Buck Switch and Driver
7.3.8
Synchronous Rectifier
7.3.9
Enable/Undervoltage Lockout (EN/UVLO)
7.3.10
Power Good (PGOOD)
7.3.11
Thermal Protection
7.4
Device Functional Modes
7.4.1
Shutdown Mode
7.4.2
Active Mode
7.4.3
Sleep Mode
8
Application and Implementation
8.1
Application Information
8.1.1
High Temperature Specifications
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Custom Design With WEBENCH® Tools
8.2.2.2
Switching Frequency (RRON)
8.2.2.3
Buck Inductor (LO)
8.2.2.4
Output Capacitor (COUT)
8.2.2.5
Input Capacitor (CIN)
8.2.2.6
Type 3 Ripple Network
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.1.1
Compact PCB Layout for EMI Reduction
8.4.1.2
Feedback Resistors
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Device Support
9.1.1
サード・パーティ製品に関する免責事項
9.1.2
Development Support
9.1.2.1
Custom Design with WEBENCH® Tools
9.2
Documentation Support
9.2.1
Related Documentation
9.3
ドキュメントの更新通知を受け取る方法
9.4
サポート・リソース
9.5
Trademarks
9.6
静電気放電に関する注意事項
9.7
用語集
10
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DDA|8
MPDS092F
サーマルパッド・メカニカル・データ
DDA|8
PPTD178C
発注情報
jajsie2a_oa
jajsie2a_pm
7.4
Device Functional Modes