JAJSKV7A June   2021  – September 2022 LM5168-Q1 , LM5169-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Control Architecture
      2. 8.3.2  Internal VCC Regulator and Bootstrap Capacitor
      3. 8.3.3  Internal Soft Start
      4. 8.3.4  On-Time Generator
      5. 8.3.5  Current Limit
      6. 8.3.6  N-Channel Buck Switch and Driver
      7. 8.3.7  Synchronous Rectifier
      8. 8.3.8  Enable, Undervoltage Lockout (EN/UVLO)
      9. 8.3.9  Power Good (PGOOD)
      10. 8.3.10 Thermal Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
      3. 8.4.3 Sleep Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Fly-Buck™ Converter Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Switching Frequency (RT)
        2. 9.2.2.2  Transformer Selection
        3. 9.2.2.3  Output Capacitor Selection
        4. 9.2.2.4  Secondary Output Diode
        5. 9.2.2.5  Setting Output Voltage
        6. 9.2.2.6  Input Capacitor
        7. 9.2.2.7  Type-3 Ripple Network
        8. 9.2.2.8  CBST Selection
        9. 9.2.2.9  Minimum Secondary Output Load
        10. 9.2.2.10 Example Design Summary
      3. 9.2.3 Application Curves
    3. 9.3 Typical Buck Application
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Switching Frequency (RT)
        2. 9.3.2.2 Buck Inductor Selection
        3. 9.3.2.3 Setting the Output Voltage
        4. 9.3.2.4 Type-3 Ripple Network
        5. 9.3.2.5 Output Capacitor Selection
        6. 9.3.2.6 Input Capacitor Considerations
        7. 9.3.2.7 CBST Selection
        8. 9.3.2.8 Example Design Summary
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Thermal Considerations
      2. 9.5.2 Typical EMI Results
      3. 9.5.3 Layout Guidelines
        1. 9.5.3.1 Compact PCB Layout for EMI Reduction
        2. 9.5.3.2 Feedback Resistors
      4. 9.5.4 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.7 Type-3 Ripple Network

A Type 3 ripple generation network uses an RC filter consisting of RA and CA across SW and VOUT1 to generate a triangular ramp that is in phase with the inductor current. This triangular ramp is then AC-coupled into the feedback node through capacitor CB. Type 3 ripple injection is suited for applications where low output voltage ripple is crucial, and is chosen for this example.

Equation 30 is used to calculate CA. With the values used in this example, CA > 245 pF. A value of 3300 pF is selected to keep RA within practical limits. In general, the user needs 20 mV of ripple at the feedback pin for reliable operation, calculated at nominal input voltage. The minimum value of ripple must not be less than 12 mV at minimum input voltage. Using Equation 31 with nominal input voltage, a value of RA > 117 kΩ was found and a value of 118 kΩ is selected.

Equation 20.
Equation 21.

While the magnitude of the generated ripple does not affect the output voltage ripple, it produces a DC error of approximately half the amplitude of the generated ripple, scaled by the feedback divider ratio. Therefore, the amount of DC offset, tolerable in the output voltage, imposes an upper bound on the feedback ripple.

Finally, Equation 32 is used to calculate the coupling capacitance CB. In the equation, TR is the approximate settling time of the control loop to a load transient disturbance. This was taken as 50 μs.

Equation 22.

where

  • TR = 50 μs (typical)

In this example, a value of > 37 pF was calculated for CB and a value of 56 pF is selected. This value avoids excessive coupling capacitor discharge by the feedback resistors during sleep intervals when operating at light loads. Note that the minimum value of CB is 47 pF.