PCB layout is a critical portion of good power supply design. There are several paths that conduct high slew-rate currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or degrade the power supply performance.

• Bypass the VIN pin to GND with a low-ESR ceramic bypass capacitor with a high-quality dielectric to help eliminate these problems. Place C_IN as close as possible to the LM516x VIN and GND pins. Grounding for both the input and output capacitors must consist of localized top-side planes that connect to the GND pin and GND PAD.
• Minimize the loop area formed by the input capacitor connections to the VIN and GND pins. The input capacitor is part of the buck converter high di/dt current loop. The high di/dt current, together with excessive parasitic inductance between the IC and the input capacitor, can result in excessive voltage ringing on the SW node of the IC. The placement of the input capacitor on the board is critical for minimizing the parasitic inductance in the high di/dt loop and accordingly minimizing the SW node ringing at each switching. For designs targeting the maximum operating voltage of the regulator, make sure the ringing on the SW node must not exceed the abs max rating of the device. The SW node ringing is a function of how well the input capacitor is positioned with respect to the IC. Refer to the PCB layout examples in Figure 8-41 and Figure 8-42 for proper placement of the input capacitors.
• Locate the inductor close to the SW pin. Minimize the area of the SW trace or plane to prevent excessive capacitive coupling.
• Tie the GND pin directly to the power pad under the device and to a heat-sinking PCB ground plane.
• Use a ground plane in one of the middle layers as a noise shielding and heat dissipation path.
• Have a single-point ground connection to the plane. Route the ground connections for the feedback, and enable components to the ground plane. This prevents any switched or load currents from flowing in analog ground traces. If not properly handled, poor grounding results in degraded load regulation or erratic output voltage ripple behavior.
• Make V_IN, V_OUT, and ground bus connections as wide as possible. This reduces any voltage drops on the input or output paths of the converter and maximizes efficiency.
• Minimize trace length to the FB pin. Place both feedback resistors, R_FB1 and R_FB2, close to the FB pin. Place C_FF (if used) directly in parallel with R_FB1. If output set-point accuracy at the load is important, connect the V_OUT sense at the load. Route the V_OUT sense path away from noisy nodes and preferably through a layer on the other side of a grounded shielding layer.
• Note that the R_T pin is sensitive to noise. Thus, locate the R_T resistor as close as possible to the device and route with minimal lengths of trace. The parasitic capacitance from RT to GND must not exceed 20 pF.
• Provide adequate heat sinking for the LM516x to keep the junction temperature below 150°C. For operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-sinking vias to connect the exposed pad to the PCB ground plane. If the PCB has multiple copper layers, these thermal vias must also be connected to inner layer heat-spreading ground planes.