JAJSG34B September   2018  – August 2021 LM5176-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency Valley/Peak Current Mode Control with Slope Compensation
      2. 7.3.2  VCC Regulator and Optional BIAS Input
      3. 7.3.3  Enable/UVLO
      4. 7.3.4  Soft-Start
      5. 7.3.5  Overcurrent Protection
      6. 7.3.6  Average Input/Output Current Limiting
      7. 7.3.7  Operation Above 40-V Input
      8. 7.3.8  CCM Operation
      9. 7.3.9  Frequency and Synchronization (RT/SYNC)
      10. 7.3.10 Frequency Dithering
      11. 7.3.11 Output Overvoltage Protection (OVP)
      12. 7.3.12 Power Good (PGOOD)
      13. 7.3.13 Gm Error Amplifier
      14. 7.3.14 Integrated Gate Drivers
      15. 7.3.15 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown, Standby, and Operating Modes
      2. 7.4.2 MODE Pin Configuration
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design with WEBENCH Tools
        2. 8.2.2.2  Frequency
        3. 8.2.2.3  VOUT
        4. 8.2.2.4  Inductor Selection
        5. 8.2.2.5  Output Capacitor
        6. 8.2.2.6  Input Capacitor
        7. 8.2.2.7  Sense Resistor (RSENSE)
        8. 8.2.2.8  Slope Compensation
        9. 8.2.2.9  UVLO
        10. 8.2.2.10 Soft-Start Capacitor
        11. 8.2.2.11 Dither Capacitor
        12. 8.2.2.12 MOSFETs QH1 and QL1
        13. 8.2.2.13 MOSFETs QH2 and QL2
        14. 8.2.2.14 Frequency Compensation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design with WEBENCH Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Inductor Selection

The inductor selection is based on consideration of both buck and boost modes of operation. For buck mode, inductor selection is based on limiting the peak-to-peak current ripple, ΔIL, to approximately 40% of the maximum inductor current at the maximum input voltage. The target inductance for buck mode is:

Equation 13. GUID-AFAC36B3-B25C-4C3F-9197-78619098D4F6-low.gif

For boost mode, the inductor selection is based on limiting the peak to peak current ripple, ΔIL, to approximately 30% of the maximum inductor current at the minimum input voltage. The target inductance for the boost mode is:

Equation 14. GUID-E65966C2-DBE3-470E-814A-2BBAFCC86680-low.gif

In this particular application, the buck inductance is larger. Choosing a larger inductance reduces the ripple current but also increases the size of the inductor. A larger inductor also reduces the achievable bandwidth of the converter by moving the right half plane zero to lower frequencies. Therefore, a judicious compromise should be made based on the application requirements. For this design, a 4.7-µH inductor is selected. With this inductor selection, the inductor current ripple is 6.5 A, 4.3 A, and 2.1 A, at VIN of 50 V, 24 V, and 6 V, respectively.

The maximum average inductor current occurs at the minimum input voltage and maximum load current:

Equation 15. GUID-245FDCD8-8EFD-4D2A-BEE1-E4BEC2FBADCD-low.gif

where

  • 90% efficiency is assumed

The peak inductor current occurs at minimum input voltage and is given by:

Equation 16. GUID-536FFEDB-3C52-410C-98FF-D3F6B49D2B01-low.gif

To ensure sufficient output current, the current limit threshold must be set to allow the maximum load current in boost operation. The inductor peak current during overload depends on the current limit resistor, RSENSE (refer to the subsection on selecting RSENSE). The peak inductor current in current limit when in boost mode is given by:

Equation 17. GUID-374588CA-F96C-47FB-A562-35EFC050EAC2-low.gif

The peak inductor current in current limit when in buck mode happens at high input voltage and is given by:

Equation 18. GUID-AE1614E4-A37E-46A0-99CD-5EA9280EBA6D-low.gif

The peak inductor current in current limit is 15 A and 16.5 A in boost mode and buck mode, respectively. The inductor should be selected to handle this current.