JAJSOR1E June   2022  – August 2024 LM5177

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Gate Driver Rise Time and Fall Time
    2. 6.2 Gate Driver Dead (Transition) Time
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-On Reset (POR System)
      2. 7.3.2  Buck-Boost Control Scheme
        1. 7.3.2.1 Boost Mode
        2. 7.3.2.2 Buck Mode
        3. 7.3.2.3 Buck-Boost Mode
      3. 7.3.3  Power Save Mode
      4. 7.3.4  Supply Voltage Selection – VMAX Switch
      5. 7.3.5  Enable and Undervoltage Lockout
      6. 7.3.6  Oscillator Frequency Selection
      7. 7.3.7  Frequency Synchronization
      8. 7.3.8  Voltage Regulation Loop
      9. 7.3.9  Output Voltage Tracking
      10. 7.3.10 Slope Compensation
      11. 7.3.11 Configurable Soft Start
      12. 7.3.12 Peak Current Sensor
      13. 7.3.13 Current Monitoring and Current Limit Control Loop
      14. 7.3.14 Short Circuit - Hiccup Protection
      15. 7.3.15 nFLT Pin and Protections
      16. 7.3.16 Device Configuration Pin
      17. 7.3.17 Dual Random Spread Spectrum – DRSS
      18. 7.3.18 Gate Driver
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design with WEBENCH Tools
        2. 8.2.2.2  Frequency
        3. 8.2.2.3  Feedback Divider
        4. 8.2.2.4  Inductor and Current Sense Resistor Selection
        5. 8.2.2.5  Slope Compensation
        6. 8.2.2.6  Output Capacitor
        7. 8.2.2.7  Input Capacitor
        8. 8.2.2.8  UVLO Divider
        9. 8.2.2.9  Soft-Start Capacitor
        10. 8.2.2.10 MOSFETs QH1 and QL1
        11. 8.2.2.11 MOSFETs QH2 and QL2
        12. 8.2.2.12 Frequency Compensation
        13. 8.2.2.13 External Component Selection
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Bi-Directional Power Backup
      2. 8.3.2 Parallel (Multiphase) Operation
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Stage Layout
      2. 10.1.2 Gate Driver Layout
      3. 10.1.3 Controller Layout
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design with WEBENCH Tools
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions


LM5177 38-Pin DCP HTSSOP Pin Diagram

Figure 4-1 38-Pin DCP HTSSOP Pin Diagram
Table 4-1 Pin Functions LM5177
Pin Type(1) Description
Name No.
AGND 17 G Analog ground of the device
BIAS 1 I Optional input to the VCC bias regulator. Powering VCC from an external supply instead of VIN can reduce power loss at high VIN.

If the bias pin supply is not used in the application connect the pin GND
CFG 13 I/O Device configuration pin. Connect a resistor between the CFG pin to select the device operation for spread spectrum (DRSS), short circuit protection (hiccup mode), current limit, or current monitor.
COMP 18 O Output of the error amplifier. An external RC network connected between COMP and AGND compensates the regulator of the output voltage feedback loop.
CSA 37 I Inductor peak current sensor positive input. Connect CSA to the positive side of the external current sense resistor using a low-current Kelvin connection.
CSB 38 I Inductor peak current sense negative input. Connect CSB to the negative side of the external current sense resistor using a low-current Kelvin connection.
DTRK 10 I Digital PWM input pin for the dynamical output voltage tracking. Do not leave this pin floating. If this function is not used, connect the pin to VCC or GND.
EN/UVLO 4 I Enable pin. The pin enables or disables the device. If the pin is less than 0.6 V, the device shuts down. The pin must be raised above 0.65 V to enable the device. This pin is the enable pin for the device internal reference circuit and input voltage UVLO comparator input.
FB 19 I Feedback pin for output voltage regulation. Connect a resistor divider network from the output of the converter to the FB pin.
HB1 35 P Bootstrap supply pin for buck half-bridge. An external capacitor is required between the HB1 pin and the SW1 pin, respectively, to provide bias to the high-side MOSFET gate driver.
HO1 34 O High-side gate driver output for the buck half-bridge
HO1_LL 8 O Logic level output of the HO1 gate signal. Connect this ground reference PWM signal to an optional external gate-driver input. If the function is not used, make no external connection to this pin.
HB2 26 P Bootstrap supply pin for boost half-bridge. An external capacitor is required between the HB2 pin and the SW2 pin, respectively, to provide bias to the high-side MOSFET gate driver.
HO2 27 O High-side gate driver output for the boost half-bridge
HO2_LL 9 O Logic level output of the HO2 gate signal. Connect this ground reference PWM signal to an optional external gate-driver input. If the function is not used, make no external connection to this pin.
IMONOUT 6 O Current monitor output pin. Output of the voltage-controlled current source of the optional current monitor. Connect the pin to a resistor to sense the voltage across. If the output or input current sense amplifier is configured as current limiter, an external RC network connected between IMONOUT and AGND compensates the regulator of the current feedback loop.

Connect the IMONOUT pin to VCC to disable the block and reduce the quiescent current

ISNSN 22 I Negative sense input of the output or input current sense amplifier. An optional current sense resistor connected between ISNSN and ISNSP can be located either on the input side or on the output side of the power stage.

In case the current monitor is disabled connect ISNSN to ground
ISNSP 23 I Positive sense input of the output or input current sense amplifier. An optional current sense resistor connected between ISNSN and ISNSP can be located either on the input side or on the output side of the power stage.

In case the current monitor is disabled connect ISNSN to ground
LO1 32 O Low-side gate driver output for the buck half-bridge
LO2 29 O Low-side gate driver output for the boost half-bridge
MODE 12 I Digital input to select device operation mode. If the pin is pulled low, power save mode (PSM) is enabled. If the pin is pulled high, the forced PWM or CCM operation is enabled. The configuration can be changed dynamically during operation. Do not leave this pin floating.
NC 2 NC No internal connection
NC 5 NC No internal connection
NC 21 NC No internal connection
NC 24 NC No internal connection
NC 28 NC No internal connection
NC 33 NC No internal connection
nFLT 7 O Open-drain output pin for fault indication or power good. This pin is pulled low when FB is outside a ±10% regulation window around the regulation window of the nominal output voltage.

If the nFLT pin function is not used the pin can be kept floating.
PowerPAD PAD G Connect the PowerPAD to the analog ground. Use thermal vias to connect to a PCB ground plane for improved power dissipation.
PGND 30 G Power ground. This pin is the high current ground connection to the low-side gate drivers and for the internal VCC regulator.
RT 15 I/O Switching frequency programming pin. An external resistor is connected to the RT pin and AGND to set the switching frequency.
SLOPE 14 I A resistor connected between the SLOPE pin and AGND provides the slope compensation ramp for stable current mode operation in both buck and boost mode.
SS/ATRK 16 I/O Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start time. Analog output voltage tracking pin. The VOUT regulation target can be programmed by connecting the pin to variable voltage reference (for example, through a digital to analog converter). The internal circuit selects the lowest voltage applied to the pin.
SW1 36 P Inductor switch node for the buck half-bridge
SW2 25 P Inductor switch node for the boost half-bridge
SYNC 11 I Synchronization clock input. The internal oscillator can be synchronized to an external clock during operation. If the output or input current sense amplifier is configured as a current limiter pulling, this pin is low during start-up, device switches the current limit direction to a negative polarity. Do not leave this pin floating. If this function is not used, connect the pin to VCC.
VCC 31 P Internal linear bias regulator output. Connect a ceramic decoupling capacitor from VCC to PGND.
VIN 3 I The input supply and sense input of the device. Connect VIN to the supply voltage of the power stage.
VOUT 20 I VOUT sense input. Connect to the power stage output rail.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect