JAJSOR1E June   2022  – August 2024 LM5177

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Gate Driver Rise Time and Fall Time
    2. 6.2 Gate Driver Dead (Transition) Time
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-On Reset (POR System)
      2. 7.3.2  Buck-Boost Control Scheme
        1. 7.3.2.1 Boost Mode
        2. 7.3.2.2 Buck Mode
        3. 7.3.2.3 Buck-Boost Mode
      3. 7.3.3  Power Save Mode
      4. 7.3.4  Supply Voltage Selection – VMAX Switch
      5. 7.3.5  Enable and Undervoltage Lockout
      6. 7.3.6  Oscillator Frequency Selection
      7. 7.3.7  Frequency Synchronization
      8. 7.3.8  Voltage Regulation Loop
      9. 7.3.9  Output Voltage Tracking
      10. 7.3.10 Slope Compensation
      11. 7.3.11 Configurable Soft Start
      12. 7.3.12 Peak Current Sensor
      13. 7.3.13 Current Monitoring and Current Limit Control Loop
      14. 7.3.14 Short Circuit - Hiccup Protection
      15. 7.3.15 nFLT Pin and Protections
      16. 7.3.16 Device Configuration Pin
      17. 7.3.17 Dual Random Spread Spectrum – DRSS
      18. 7.3.18 Gate Driver
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design with WEBENCH Tools
        2. 8.2.2.2  Frequency
        3. 8.2.2.3  Feedback Divider
        4. 8.2.2.4  Inductor and Current Sense Resistor Selection
        5. 8.2.2.5  Slope Compensation
        6. 8.2.2.6  Output Capacitor
        7. 8.2.2.7  Input Capacitor
        8. 8.2.2.8  UVLO Divider
        9. 8.2.2.9  Soft-Start Capacitor
        10. 8.2.2.10 MOSFETs QH1 and QL1
        11. 8.2.2.11 MOSFETs QH2 and QL2
        12. 8.2.2.12 Frequency Compensation
        13. 8.2.2.13 External Component Selection
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Bi-Directional Power Backup
      2. 8.3.2 Parallel (Multiphase) Operation
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Stage Layout
      2. 10.1.2 Gate Driver Layout
      3. 10.1.3 Controller Layout
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design with WEBENCH Tools
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.15 nFLT Pin and Protections

The open-drain nFLT ouput directly follows the input signals of monitoring features. For instance if the power good flag triggers by Vo falling below the power good threshold the nFLT pins pulls low. After a power-cycle of the device or in case the internal failure signal disappears the nFLT pin will go back to HighZ. The input signals to the nFLT pin are digitally de-glitched. Due to this the maximum reaction time of the FLT pin is given by td(nFLT-PIN)

LM5177 Functional Block Diagram nFLT-pin Logic Figure 7-18 Functional Block Diagram nFLT-pin Logic

Thermal Shutdown (TSD)

To avoid the case of a thermal damage of the device the die temperature of the die is monitored. The device will stop operation once the sensed temperature rises over the thermal shutdown threshold. After the temperature drops below the thermal shutdown hysteresis the TSD signal goes back to normal and the converter will return to normal operation according to the main FSM definition.

Over Current or Short Circuit Protection

The device features a hiccup mode short circuit protection to avoid excessive power dissipation in the die or at the fault of the application in the System. The OCP triggers if the peak current sensing voltage between CSA-pin and CSB-pin is exceeded.

The protection feature will stop and restart the converter operation in case of a short is event is detected.

Output Over Voltage Protection 1 (OVP1)

This over voltage protection monitors the voltage of the FB-pin.

As this threshold is referenced to the V(REF) the OVP1 continues its operation even if of tracking features has changed the Vo target value.

The converter maintains in regulation even the OVP1 threshold triggers.

The OVP1 is disabled during PSM to avoid additional leakage current. The OVP signal gets masked to avoid that a fault is indicated from this signal during the PSM operation.

This protection is disabled during the soft-start procedure.

Output Over Voltage protection 2 (OVP2)

This feature shall avoid any damage to the device in case the external feedback pin is not working properly i.e. is shorted to GND

If the output voltage threshold VT+(OVP2) is reached on the VOUT-pin the buck-boost core logic disables the converter power stage and enters a high impedance state at the switch nodes. If the output voltage falls back under this threshold the convert operation is resumed.

Input Voltage Protection (IVP)

The input over voltage protection is part of the converter core modulation scheme. The IVP avoids any damage to the device in case the current flows from the output to the input and the input source can not sink current e.g. there is a diode in the supply path. If the converter forced PWM mode is active the current can go negative until the sink current limit. Once the input voltage threshold VT+(IVP) is reach on the VIN-pin the protection disables the forced PWM mode and only allows current to flow from VIN to VOUT. After the input voltage drops under the input voltage protection threshold, the fPWM mode activates again.

Power Good

The device features a power good detection. The FB pin voltages gets contentiously monitors. If the sensed voltage drops below the PG falling threshold the signal is pulling low the nFLT pin.

This protection is disabled during the soft-start procedure.

Boot-strap Under Voltage Protection

The high side supply voltage for the gate driver are monitored by an UVLO comparator (BST_UV). This comparator monitors the differential voltage between SWx pin and HBx pin. If the measured voltage drops below VTH-(BST_UV) the converter stops operation

Boot-strap Over Voltage Clamp

To protect the internal gate driver circuit the external FET gates and the internal circuit features an over voltage clamp. If the voltage goes above VTH(BST_OV) the linear regulator sinks a current from HBx pin to SWx-pin as long as the voltage is above the threshold.