JAJSOR1E June   2022  – August 2024 LM5177

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Gate Driver Rise Time and Fall Time
    2. 6.2 Gate Driver Dead (Transition) Time
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-On Reset (POR System)
      2. 7.3.2  Buck-Boost Control Scheme
        1. 7.3.2.1 Boost Mode
        2. 7.3.2.2 Buck Mode
        3. 7.3.2.3 Buck-Boost Mode
      3. 7.3.3  Power Save Mode
      4. 7.3.4  Supply Voltage Selection – VMAX Switch
      5. 7.3.5  Enable and Undervoltage Lockout
      6. 7.3.6  Oscillator Frequency Selection
      7. 7.3.7  Frequency Synchronization
      8. 7.3.8  Voltage Regulation Loop
      9. 7.3.9  Output Voltage Tracking
      10. 7.3.10 Slope Compensation
      11. 7.3.11 Configurable Soft Start
      12. 7.3.12 Peak Current Sensor
      13. 7.3.13 Current Monitoring and Current Limit Control Loop
      14. 7.3.14 Short Circuit - Hiccup Protection
      15. 7.3.15 nFLT Pin and Protections
      16. 7.3.16 Device Configuration Pin
      17. 7.3.17 Dual Random Spread Spectrum – DRSS
      18. 7.3.18 Gate Driver
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design with WEBENCH Tools
        2. 8.2.2.2  Frequency
        3. 8.2.2.3  Feedback Divider
        4. 8.2.2.4  Inductor and Current Sense Resistor Selection
        5. 8.2.2.5  Slope Compensation
        6. 8.2.2.6  Output Capacitor
        7. 8.2.2.7  Input Capacitor
        8. 8.2.2.8  UVLO Divider
        9. 8.2.2.9  Soft-Start Capacitor
        10. 8.2.2.10 MOSFETs QH1 and QL1
        11. 8.2.2.11 MOSFETs QH2 and QL2
        12. 8.2.2.12 Frequency Compensation
        13. 8.2.2.13 External Component Selection
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Bi-Directional Power Backup
      2. 8.3.2 Parallel (Multiphase) Operation
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Stage Layout
      2. 10.1.2 Gate Driver Layout
      3. 10.1.3 Controller Layout
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design with WEBENCH Tools
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

Typical values correspond to TJ=25°C. Minimum and maximum limits apply over TJ=-40°C to 125℃. Unless otherwise stated, V(BIAS) =12 V
PARAMETER MIN TYP MAX UNIT
SUPPLY CURRENT
Shutdown current into VIN V(VIN) = 12 V,  V(BIAS) = 0 V V(EN) = 0 V TJ = 25°C 2.8 4 µA
TJ = –40°C to 125°C 2.8 5 µA
Shutdown current into BIAS  V(VIN) = 0 V,  V(EN) = 0 V TJ = 25°C 2.8 4 µA
TJ = –40°C to 125°C 2.8 5 µA
Quiescent current into BIAS  V(EN) = 3.3 V, V(FB) > 1 V,   TJ = 25°C 60 80 µA
TJ = –40°C to 125°C 60 90 µA
IIL Low-level input current (EN/UVLO) V(EN/UVLO) ≤ 0.55 V
 		 ±0.01 ±0.1 µA
VCC REGULATOR
VCC regulation VBIAS 12.0 V ,I(VCC) = 20 mA 4.75 5 5.25 V
VVIN  12.0 V ,I(VCC) = 20 mA 4.75 5 5.25 V
VCC line regulation I(VCC) = 1 mA V(VIN) =3.5V  V(BIAS) = 6.7 V to 42 V ±1 %
V(BIAS) =0 V  V(VIN) = 6.7 V to 78 V ±1 %
BIAS LDO dropout load regulation V(BIAS)= 6.7V, V(VIN) = 3.5 V, I(VCC) = 1 mA to 200 mA 65 120 mV
VBIAS = 3.5V, V(VIN) = 2.8 V, I(VCC) = 35 mA 200 mV
VIN LDO dropout load regulation V(BIAS)= 0V, V(VIN) = 6.7V, I(VCC) = 1 mA to 175 mA 65 120 mV
V(BIAS)= 0V, V(VIN) = 3.5V, I(VCC) =  15 mA 89 200 mV
VCC UVLO delay VCC rising 6 us
VCC sourcing current limit VCC ≥ 4.5 V V(BIAS)= 0V, V(VIN) = 12 V, 200 mA
V(VIN) = 3.5 V, 200 mA
VT+(VCC) Positive going threshold  V(VCC) rising 3.4 3.45 3.5 V
VT-(VCC) Negative going threshold  V(VCC) falling 3.2 3.25 3.3 V
VT+(VCC,SUP) Positive going threshold for LDO switch-over  6.35 6.5 6.7 V
Vhyst(VCC,SUP) LDO switch-over hysteresis   60 mV
ENABLE
VT+(EN) Enable positive-going threshold  EN rising 0.47 0.63 0.8 V
VT-(EN) Enable negative-going threshold  EN falling 0.45 0.6 0.75 V
Vhyst(EN) Enable threshold hysteresis EN falling 20 100 mV
td(EN) Shutdown delay time  14 20 us
UVLO
VDET positive-going threshold  V(VIN) rising 3.3 3.4 3.55 V
VDET negative-going threshold  V(VIN) falling 2.6 2.7 2.85 V
VT+(UVLO) UVLO positive-going threshold  V(EN/UVLO) rising 1.22 1.25  1.28 V
VT-(UVLO) UVLO negative-going threshold  V(EN/UVLO) falling 1.17 1.2 1.23 V
IUVLO UVLO hysteresis sinking current 0.7 V ≤ V(EN/UVLO) < 1.22 V 4 5 6 µA
Enable time to start switching VCC = 5V, VT+(UVLO) > 1.3V 45 us
td(UVLO) UVLO and VDET detection delay time  V(EN/UVLO) falling; V(VDET) falling 25.5 30 34.5 µs
SYNC
VT+(SYNC) Sync input positive going threshold 1.19 V
VT-(SYNC) Sync input negative going threshold 0.41 V
Sync activity detection frequency 99 kHz
td(Det,Sync) Sync activity detection delay referred to f(SYNC)  3 cycles
Sync PLL lock time referred to f(SYNC)  until f(SYNC) - 5% < f(sw) < f(SYNC) + 5% 10 cycles
SOFT-START
I(SS) Soft-start current 8.9 10 11 uA

SS pull-down switch RDS(on)
 		 V(SS) = 1 V 23 40 Ω
td(DISCH;SS) SS Pin discharge time  Time from internal SS discharge until the soft-start current can charge the pin again 500 µs
td(EN_SS) SS Pin charge delay time Internal delay until soft-start current starts 2.5 4 µs
V(SS,clamp) Clamp Voltage for SS pin 3 4.1 5.25 V
PULSE WIDTH MODULATION
Switching frequency RRT = 49.9 kΩ 540 600 660 kHz
Switching frequency RRT = 316 kΩ 90 100 110 kHz
Minimum controllable on-time fPWM, RRT = 49.9 kΩ Boost Mode 154 ns
Buck Mode  197 ns
Minimum controllable off-time   Boost Mode 207 ns
Buck Mode  210 ns
RT regulation voltage 0.75 V
SPREAD SPECTRUM
Switching frequency modulation range  upper limit 7.8 %
lower limit –7.8 %
VOUT TRACKING
VT+(DTRK) DTRK positive-going threshold  V(DTRK) rising 1.19 V
VT-(DTRK) DTRK negative-going threshold  V(DTRK) falling 0.41 V
DTRK activity detection frequency 148 kHz
td(Det,DTRK) DTRK activity detection delay referred to f(DTRK)  3 cycles
fc(LPF) Corner frequency of internal low pass 26 35 58 kHz
V(REF)voltage offset error  f(DTRK) = 500kHz, duty = 50% ±10 mV
MODE SELECTION
VT+(MODE) Mode input positive going threshold 1.19 V
VT-(MODE) Mode input negative going threshold 0.41 V
CURRENT SENSE
Positive peak current  limit threshold  38.5 50 58.5 mV
Negative peak current limit threshold  –61.6 –50 –40.5 mV
PSM entry threshold PSM ENTRY = 10 % 0.8 5.0 9.7 mV
PSM entry threshold PSM ENTRY = 15 % 3.3 7.5 11.2 mV
CURRENT MONITOR/LIMITER
Current sense amplifier transconductance IMON_LIMITER_EN = 0b0 0 mV ≤ ΔV(ISNS) ≤ 50 mV 0.9 1 1.1 mS
Offset voltage (1) IMON_LIMITER_EN = 0b0 TJ= 25℃ ±1 mV
Current sense amplifier bandwidth 1 2 MHz
Output current IMONOUT  IMON_LIMITER_EN = 0b0, TJ=-40°C to 125°C ΔV(IMON) = 45 mV 39 45 49.5 µA
ΔV(IMON) = 5 mV 1 5 8.1 µA
Current sense amplifier transconductance IMON_LIMITER_EN = 0b1 170 200  220 µS
ΔV(ISNS) Current sense offset and threshold voltage IMON_LIMITER_EN = 0b1 TJ= 25℃ 49 50 51.7 mV
ISNS pin input bias currents ISNSP = ISNSN = 12 V 80 115 µA
IMONOUT negative output headroom V(BIAS) > 6.5V;  I(IMONOUT )  = I(IMONOUT ) x 0.975 at  V(IMONOUT) = 1V ΔV = 50mV ,referred to VCC 300 500 mV
ΔV = –50mV, referred to GND 320 500 mV
VT+(DIS,IMON) Positive going threshold to disable IMON referred to VCC 55 65 75 %
HICCUP MODE PROTECTION 
Hiccup mode on time 1 ms
Hiccup mode off time  24 ms
ERROR AMPLIFIER
VREF FB reference Voltage FB reference 0.99 1 1.01 V
FB reference Voltage forced V(SS) = 0.95 V 0.92 0.95 0.98 V
FB pin leakage current  V(FB) = 1 V 60 nA
Transconductance 600 µS
Output resistance 13 96 MΩ
COMP sourcing current 65 150 uA
COMP sinking current 65 150 uA
COMP clamp voltage V(FB) = 990 mV 1.2 1.25 1.3 V
COMP clamp voltage V(FB) = 1.01 V 0.225 0.240 0.255 V
Unity gain bandwidth 4.5 MHz
OVP
VT+(OVP) Over-voltage rising threshold FB rising reference to VREF 107 110 115 %
VT-(OVP) Over-voltage falling threshold FB falling  reference to VREF 101 105 109 %
Over-voltage de-glitch time  9 10 12.5 µs
VT+(OVP2) Over-voltage 2 rising threshold V(VOUT) rising  80.5 83.5 86 V
Over-voltage 2 typical programming range V(VOUT) rising  3.33 83.5 V
VT+(IVP) Over-voltage rising threshold V(VIN) rising  80.5 86 V
nFLT
nFLT pull-down switch on resistance 1mA sinking 100 Ω
Power good positive going threshold FB rising (reference to VREF) 95 %
Power good negative going threshold FB falling (reference to VREF) 90 %
nFLT off-state leakage V(nFLT)=5V 100 nA
td(nFLT-PIN)  nFLT pin reaction time Measured from a fault event until nFLT goes low 37 µs
MOSFET DRIVER
tr  Rise time  HG1, HG2, LG1, LG2 CG = 3.3nF 12 ns
tf Fall time  HG1, HG2, LG1, LG2 CG = 3.3nF 12 ns
tt Dead-time  HOx from High to Low and LOx from Low to High CG = 3.3nF R(RT) =  14.7 kΩ   19 ns
HOx from Low to High and LOx from High to Low 20.5 ns
HOx from High to Low and LOx from Low to High R(RT) =  316 k Ω 21.5 ns
HOx from Low to High and LOx from High to Low 23 ns
Gate driver low side PMOS on-resistance  LO1, LO2 I(test) = 200 mA 1.6 Ω
Gate driver high side PMOS on-resistance  HO1, HO2 I(test) = 200 mA 1.3 Ω
Gate driver low side NMOS on-resistance  LO1, LO2 I(test) = 200 mA 0.6 Ω
Gate driver high side NMOS on-resistance  HO1, HO2 I(test) = 200 mA 0.7 Ω
VTH- (BST_UV) Negative going boot-strap V(HBx) - V(SWx)   falling  2.4 2.8 3.1 V
VTH+ (BST_UV) Positive going boot-strap V(HBx) - V(SWx)  rising  2.6 3 3.35 V
VTH+ (BST_OV) Positive going boot-strap over-voltage threshold Positive going boot-strap over-voltage threshold V(HBx) - V(SWx)  rising, I(HBx)=25uA  4.8 5.5 6.3 V
VTH (GATEOUT) Low/High Side Gate driver output switching detection referenced to VCC  37 %
referenced to V(HBx) - V(SWx) 37 %
THERMAL SHUTDOWN
TT+J   Thermal shutdown threshold   Thermal shutdown threshold TJ rising 164 °C
Thermal shutdown hysteresis Thermal shutdown hysteresis 15 °C
R2D INTERFACE
Internal reference resistor 31.77 33 34.23 kΩ
RCFG External selection resistor resistance R2D setting #0 0 0.1 kΩ
R2D setting #1 0.49567 0.511 0.52633 kΩ
R2D setting #2 1.1155 1.15 1.1845 kΩ
R2D setting #3 1.8139 1.87 1.9261 kΩ
R2D setting #4 2.6578 2.74 2.8222 kΩ
R2D setting #5 3.7151 3.83 3.9449 kΩ
R2D setting #6 4.9567 5.11 5.2633 kΩ
R2D setting #7 6.2953 6.49 6.6847 kΩ
R2D setting #8 8.0025 8.25 8.4975 kΩ
R2D setting #9 10.185 10.5 10.815 kΩ
R2D setting #10 12.901 13.3 13.699 kΩ
R2D setting #11 15.714 16.2 16.686 kΩ
R2D setting #12 19.885 20.5 21.115 kΩ
R2D setting #13 24.153 24.9 25.647 kΩ
R2D setting #14 29.197 30.1 31.003 kΩ
R2D setting #15 35.405 36.5 37.595 kΩ
(1) Zero Offset is determined by interpolation