JAJSP12 データシート

JAJSP12 July 2024 LM5190-Q1

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7.1.1.4 Power MOSFETs

The choice of power MOSFETs has significant impact on DC/DC regulator performance. A MOSFET with low on-state resistance, R_DS(on), reduces conduction loss, whereas low parasitic capacitances enable faster transition times and reduced switching loss. Normally, the lower the R_DS(on) of a MOSFET, the higher the gate charge and output charge (Q_G and Q_OSS, respectively), and vice versa. As a result, the product of R_DS(on) and Q_G is commonly specified as a MOSFET figure-of-merit. Low thermal resistance of a given package makes sure that the MOSFET power dissipation does not result in excessive MOSFET die temperature.

The main parameters affecting power MOSFET selection are as follows:

R_DS(on) at 7.5V.
Drain-source voltage rating, BV_DSS.
Gate charge parameters at 7.5V.
Output charge, Q_OSS, at the relevant input voltage.
Body diode reverse recovery charge, Q_RR.
Gate threshold voltage, V_GS(th), derived from the Miller plateau evident in the Q_G versus V_GS plot in the MOSFET data sheet. To enhance MOSFET adequately, the miller plateau voltage must be 2V to 3V lower than the gate drive amplitude, especially at the minimum input voltage.

The MOSFET-related power losses for one channel are summarized by the equations presented in Table 7-1, where suffixes one and two represent high-side and low-side MOSFET parameters, respectively. While the influence of inductor ripple current is considered, second-order loss modes, such as those related to parasitic inductances and SW node ringing, are not included.

Table 7-1 MOSFET Power Losses

POWER LOSS MODE	HIGH-SIDE MOSFET	LOW-SIDE MOSFET
MOSFET conduction⁽²⁾⁽³⁾	Equation 20. $P_{c o n d 1} = D \times ({I_{L O A D}}^{2} + \frac{{∆ I_{L O U T}}^{2}}{12}) \times R_{D S (o n) 1}$	Equation 21. $P_{c o n d 2} = D^{'} \times ({I_{L O A D}}^{2} + \frac{{∆ I_{L O U T}}^{2}}{12}) \times R_{D S (o n) 2}$
MOSFET switching	Equation 22. $P_{s w 1} = \frac{V_{S U P P L Y} \times f_{S W}}{2} \times [(I_{L O A D} - \frac{{∆ I}_{L O U T}}{2}) \times t_{R} + (I_{L O A D} + \frac{{∆ I}_{L O U T}}{2}) \times t_{F}]$	Negligible
MOSFET gate drive⁽¹⁾	Equation 23. $P_{g a t e 1} = V_{C C} \times f_{S W} \times Q_{G 1}$	Equation 24. $P_{g a t e 2} = V_{C C} \times f_{S W} \times Q_{G 2}$
MOSFET output charge⁽⁴⁾	Equation 25. $P_{C o s s} = f_{S W} \times (V_{S U P P L Y} \times Q_{O S S 2} + E_{o s s 1} - E_{o s s 2})$
Body diode conduction	N/A	Equation 26. $P_{c o n d B D} = V_{F} \times f_{S W} \times [(I_{L O A D} + \frac{{∆ I}_{L O U T}}{2}) \times t_{d t 1} + (I_{L O A D} - \frac{{∆ I}_{L O U T}}{2}) \times t_{d t 2}]$
Body diode reverse recovery⁽⁵⁾	Equation 27. $P_{R R} = V_{S U P P L Y} \times f_{S W} \times Q_{R R 2}$

(1) Gate drive loss is apportioned based on the internal gate resistance of the MOSFET, externally added series gate resistance and the relevant driver resistance of the device.

(2) MOSFET R_DS(on) has a positive temperature coefficient of approximately 4500ppm/°C. The MOSFET junction temperature, T_J, and the rise over ambient temperature is dependent upon the device total power dissipation and the thermal impedance. When operating at or near minimum input voltage, make sure that the MOSFET R_DS(on) is rated for the available gate drive voltage.

(3) D' = 1–D is the duty cycle complement.

(4) MOSFET output capacitances, C_oss1 and C_oss2, are highly non-linear with voltage. These capacitances are charged losslessly by the inductor current at high-side MOSFET turn-off. During turn-on, however, a current flows from the input to charge the output capacitance of the low-side MOSFET. E_oss1, the energy of C_oss1, is dissipated at turn-on, but this dissipation is offset by the stored energy E_oss2 on C_oss2.

(5) MOSFET body diode reverse recovery charge, Q_RR, depends on many parameters, particularly forward current, current transition speed, and temperature.

The high-side (control) MOSFET carries the inductor current during the PWM on-time (or D interval) and typically incurs most of the switching losses. Choosing a high-side MOSFET that balances conduction and switching loss contributions is imperative. The total power dissipation in the high-side MOSFET is the sum of the losses due to conduction, switching (voltage-current overlap), output charge, and typically two-thirds of the net loss attributed to body diode reverse recovery.

The low-side (synchronous) MOSFET carries the inductor current when the high-side MOSFET is off (or 1–D interval). The low-side MOSFET switching loss is negligible as the low-side MOSFET switching loss is switched at zero voltage – current just communicates from the channel to the body diode or vice versa during the transition dead-times. The device, with the adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such losses scale directly with switching frequency.

In high step-down ratio applications, the low-side MOSFET carries the current for a large portion of the switching period. Therefore, to attain high efficiency, optimizing the low-side MOSFET for low R_DS(on) is critical. In cases where the conduction loss is too high or the target R_DS(on) is lower than available in a single MOSFET, connect two low-side MOSFETs in parallel. The total power dissipation of the low-side MOSFET is the sum of the losses due to channel conduction, body diode conduction, and typically one-third of the net loss attributed to body diode reverse recovery.