JAJSF02F October   2008  – July 2019 LM5575-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Shutdown and Standby
      2. 7.3.2 Current Limit
      3. 7.3.3 Soft Start
      4. 7.3.4 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 High-Voltage Start-Up Regulator
      2. 7.4.2 Oscillator and Sync Capability
      3. 7.4.3 Error Amplifier and PWM Comparator
      4. 7.4.4 Ramp Generator
      5. 7.4.5 BOOST Pin
      6. 7.4.6 Maximum Duty Cycle and Input Dropout Voltage
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bias Power Dissipation Reduction
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  External Components
        3. 8.2.2.3  R3 (RT)
        4. 8.2.2.4  L1
        5. 8.2.2.5  C3 (CRAMP)
        6. 8.2.2.6  C9, C10
        7. 8.2.2.7  D1
        8. 8.2.2.8  C1, C2
        9. 8.2.2.9  C8
        10. 8.2.2.10 C7
        11. 8.2.2.11 C4
        12. 8.2.2.12 R5, R6
        13. 8.2.2.13 R1, R2, C12
        14. 8.2.2.14 R7, C11
        15. 8.2.2.15 R4, C5, C6
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

PWP Package
16-Pin HTSSOP With Exposed Thermal Pad
Top View
LM5575-Q1 30070802.gif

Pin Functions

PIN I/O DESCRIPTION APPLICATION INFORMATION
NO. NAME
1 VCC O Output of the bias regulator VCC tracks VIN up to 9 V. Beyond 9 V, VCC is regulated to 7 V. A 0.1-µF to 1-µF ceramic decoupling capacitor is required. An external voltage (7.5 V – 14 V) can be applied to this pin to reduce internal power dissipation.
2 SD I Shutdown or UVLO input If the SD pin voltage is lower than 0.7 V, the regulator is in a low power state. If the SD pin voltage is between 0.7 V and 1.225 V the regulator is in standby mode. If the SD pin voltage is higher than 1.225 V, the regulator is operational. An external voltage divider can be used to set a line undervoltage shutdown threshold. If the SD pin is left open circuit, a 5-µA pullup current source configures the regulator fully operational.
3 VIN I Input supply voltage Nominal operating range: 6 V to 75 V.
4 SYNC I Oscillator synchronization input or output The internal oscillator can be synchronized to an external clock with an external pulldown device. Multiple LM5575-Q1 devices can be synchronized together by connection of their SYNC pins.
5 COMP O Output of the internal error amplifier The loop compensation network must be connected between this pin and the FB pin.
6 FB I Feedback signal from the regulated output This pin is connected to the inverting input of the internal error amplifier. The regulation threshold is 1.225 V.
7 RT I Internal oscillator frequency set input The internal oscillator is set with a single resistor connected between this pin and the AGND pin.
8 RAMP O Ramp control signal An external capacitor connected between this pin and the AGND pin sets the ramp slope used for current mode control. Recommended capacitor range 50 pF to 2000 pF.
9 AGND GND Analog ground Internal reference for the regulator control functions
10 SS O Soft start An external capacitor and an internal 10-µA current source set the time constant for the rise of the error amp reference. The SS pin is held low during standby, VCC UVLO, and thermal shutdown.
11 OUT O Output voltage connection Connect directly to the regulated output voltage.
12 PGND GND Power ground Low-side reference for the PRE switch and the IS sense resistor.
13 IS I Current sense Current measurement connection for the re-circulating diode. An internal sense resistor and a sample and hold circuit sense the diode current near the conclusion of the off-time. This current measurement provides the DC level of the emulated current ramp.
14 SW O Switching node The source terminal of the internal buck switch. Connect the SW pin to the external Schottky diode and to the buck inductor.
15 PRE O Pre-charge assist for the bootstrap capacitor This open-drain output can be connected to SW pin to help charging the bootstrap capacitor during very light load conditions or in applications where the output may be pre-charged before the LM5575-Q1 is enabled. An internal pre-charge MOSFET is turned on for 250 ns each cycle just prior to the on-time interval of the buck switch.
16 BST I Boost input for bootstrap capacitor An external capacitor is required between the BST and the SW pins. TI recommends a 0.022-µF ceramic capacitor. The capacitor is charged from VCC through an internal diode during the off-time of the buck switch.
NA EP -- Exposed Pad Exposed metal pad on the underside of the device. TI recommends to connect this pad to the PWB ground plane to help with heat dissipation.