JAJSIR9C March 2020 – June 2021 LM61440-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
EFFICIENCY | ||||||
ƞ5V_2p1MHz | Typical 2.1 MHz efficiency | VOUT = 5 V, IOUT = 4 A, RBOOT = 0 Ω | 93 | % | ||
VOUT = 5 V, IOUT = 100 µA, RBOOT = 0 Ω, RFBT = 1 MΩ | 73 | |||||
ƞ3p3V_2p1MHz | Typical 2.1 MHz efficiency | VOUT = 3.3 V, IOUT = 4 A, RBOOT = 0 Ω | 91 | % | ||
VOUT = 3.3 V, IOUT = 100 µA, RBOOT = 0 Ω, RFBT = 1 MΩ | 71 | |||||
ƞ5V_400kHz | Typical 400 kHz efficiency | VOUT = 5 V, IOUT = 4 A, RBOOT = 0 Ω | 95 | % | ||
VOUT = 5 V, IOUT = 100 µA, RBOOT = 0 Ω, RFBT = 1 MΩ | 76 | |||||
RANGE OF OPERATION | ||||||
VVIN_MIN1 | VIN for full functionality at reduced load, after start-up. | VOUT set to 3.3 V | 3.0 | V | ||
VVIN_MIN2 | VIN for full functionality at 100% of maximum rated load, after start-up. | VOUT set to 3.3 V | 3.95 | V | ||
IQ-VIN | Operating quiescent current(1) | VOUT = 3.3 V, IOUT = 0 A, Auto mode, RFBT=1 MΩ | 7 | µA | ||
VOUT = 5 V, IOUT = 0 A, Auto mode, RFBT=1 MΩ | 10 | |||||
VDROP1 | Input to output voltage differential to maintain regulation accuracy without inductor DCR drop | VOUT = 3.3 V, IOUT = 4 A, -3% output accuracy at 25℃ | 0.4 | V | ||
VOUT = 3.3 V, IOUT = 4 A, -3% output accuracy at 125℃ | 0.55 | |||||
VDROP2 | Input to output voltage differential to maintain fSW ≥ 1.85MHz, without DCR drop | VOUT = 3.3 V, IOUT = 4 A, -3% regulation accuracy at 25℃ | 0.8 | V | ||
VOUT = 3.3 V, IOUT = 4 A, -3% regulation accuracy at 125℃ | 1.2 | |||||
DMAX | Maximum switch duty cycle | fSW =1.85 MHz | 87 | % | ||
While in frequency fold back | 98 | % | ||||
RBOOT | ||||||
tRISE | SW node rise time | RBOOT = 0 Ω, IOUT = 2 A (10% to 80%) | 2.15 | ns | ||
RBOOT = 100 Ω, IOUT = 2 A (10% to 80%) | 2.7 | ns |