JAJSIT0C May   2019  – June 2021 LM61440

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Systems Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  EN/SYNC Uses for Enable and VIN UVLO
      2. 8.3.2  EN/SYNC Pin Uses for Synchronization
      3. 8.3.3  Clock Locking
      4. 8.3.4  Adjustable Switching Frequency
      5. 8.3.5  PGOOD Output Operation
      6. 8.3.6  Internal LDO, VCC UVLO, and BIAS Input
      7. 8.3.7  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
      8. 8.3.8  Adjustable SW Node Slew Rate
      9. 8.3.9  Spread Spectrum
      10. 8.3.10 Soft Start and Recovery From Dropout
      11. 8.3.11 Output Voltage Setting
      12. 8.3.12 Overcurrent and Short Circuit Protection
      13. 8.3.13 Thermal Shutdown
      14. 8.3.14 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 CCM Mode
        2. 8.4.3.2 Auto Mode - Light Load Operation
          1. 8.4.3.2.1 Diode Emulation
          2. 8.4.3.2.2 Frequency Reduction
        3. 8.4.3.3 FPWM Mode - Light Load Operation
        4. 8.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Choosing the Switching Frequency
        2. 9.2.2.2  Setting the Output Voltage
        3. 9.2.2.3  Inductor Selection
        4. 9.2.2.4  Output Capacitor Selection
        5. 9.2.2.5  Input Capacitor Selection
        6. 9.2.2.6  BOOT Capacitor
        7. 9.2.2.7  BOOT Resistor
        8. 9.2.2.8  VCC
        9. 9.2.2.9  BIAS
        10. 9.2.2.10 CFF and RFF Selection
        11. 9.2.2.11 External UVLO
      3. 9.2.3 Application Curves
      4. 9.2.4 USB Type-C System Example
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground and Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-8F0200C9-48B8-4134-A3FC-7B2790D56B2C-low.gif Figure 6-1 14-Pin VQFN-HR RJR Package Top View
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
BIAS 1 P Input to internal LDO. Connect to output voltage point to improve efficiency. Connect an optional high quality 0.1-µF to 1-µF capacitor from this pin to ground for improved noise immunity. If output voltage is above 12 V, connect this pin to ground.
VCC 2 O Internal LDO output. Used as supply to internal control circuits. Do not connect to any external loads. Connect a high-quality 1-µF capacitor from this pin to AGND.
AGND 3 G Analog ground for internal circuitry. Feedback and VCC are measured with respect to this pin. Must connect AGND to both PGND1 and PGND2 on PCB.
FB 4 I Output voltage feedback input to the internal control loop. Connect to feedback divider tap point for adjustable output voltage. Do not float or connect to ground.
PGOOD 5 O Open-drain power-good status output. Pull this pin up to a suitable voltage supply through a current limiting resistor. High = power OK, low = fault. PGOOD output goes low when EN = low, VIN > 1 V.
RT 6 I/O Connect this pin to ground through a resistor with value between 5.76 kΩ and 66.5 kΩ to set switching frequency between 200 kHz and 2200 kHz. Do not float or connect to ground.
EN/SYNC 7 I Precision enable input. High = on, Low = off. Can be connected to VIN. Precision enable allows the pin to be used as an adjustable UVLO. See Section 9. Do not float. EN/SYNC also functions as a synchronization input pin. Used to synchronize the device switching frequency to a system clock. Triggers on rising edge of external clock. A capacitor can be used to AC couple the synchronization signal to this pin. When synchronized to external clock, the device functions in forced PWM and disables the PFM light load efficiency mode. See Section 8.
VIN1 8 P Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin to PGND1. Low impedance connection must be provided to VIN2.
PGND1 9 G Power ground to internal low-side MOSFET. Connect to system ground. Low impedance connection must be provided to PGND2. Connect a high-quality bypass capacitor or capacitors from this pin to VIN1.
SW 10 O Switch node of the converter. Connect to output inductor.
PGND2 11 G Power ground to internal low-side MOSFET. Connect to system ground. Low impedance connection must be provided to PGND1. Connect a high-quality bypass capacitor or capacitors from this pin to VIN2.
VIN2 12 P Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin to PGND2. Low impedance connection must be provided to VIN1.
RBOOT 13 I/O Connect to CBOOT through a resistor. This resistance must be between 0 Ω and open and determines SW node rise time.
CBOOT 14 I/O High-side driver upper supply rail. Connect a 100-nF capacitor between SW pin and CBOOT. An internal diode connects to VCC and allows CBOOT to charge while SW node is low.