JAJSJT2D February   2020  – August 2021 LM61480-Q1 , LM61495-Q1 , LM62460-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 System Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Output Voltage Selection
      2. 8.3.2  Enable EN Pin and Use as VIN UVLO
      3. 8.3.3  SYNC/MODE Uses for Synchronization
      4. 8.3.4  Clock Locking
      5. 8.3.5  Adjustable Switching Frequency
      6. 8.3.6  RESET Output Operation
      7. 8.3.7  Internal LDO, VCC UVLO, and BIAS Input
      8. 8.3.8  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
      9. 8.3.9  Adjustable SW Node Slew Rate
      10. 8.3.10 Spread Spectrum
      11. 8.3.11 Soft Start and Recovery From Dropout
      12. 8.3.12 Overcurrent and Short Circuit Protection
      13. 8.3.13 Hiccup
      14. 8.3.14 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 Peak Current Mode Operation
        2. 8.4.3.2 Auto Mode Operation
          1. 8.4.3.2.1 Diode Emulation
        3. 8.4.3.3 FPWM Mode Operation
        4. 8.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
        6. 8.4.3.6 Recovery from Dropout
        7. 8.4.3.7 Other Fault Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Choosing the Switching Frequency
        2. 9.2.2.2  Setting the Output Voltage
        3. 9.2.2.3  Inductor Selection
        4. 9.2.2.4  Output Capacitor Selection
        5. 9.2.2.5  Input Capacitor Selection
        6. 9.2.2.6  BOOT Capacitor
        7. 9.2.2.7  BOOT Resistor
        8. 9.2.2.8  VCC
        9. 9.2.2.9  CFF and RFF Selection
        10. 9.2.2.10 RSPSP Selection
        11. 9.2.2.11 RT Selection
        12. 9.2.2.12 RMODE Selection
        13. 9.2.2.13 External UVLO
        14. 9.2.2.14 Maximum Ambient Temperature
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground and Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Glossary
    6. 12.6 Electrostatic Discharge Caution
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise noted. Minimum and Maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 13.5V. VIN1 shorted to VIN2 = VIN. VOUT is output set point.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VIN Minimum operating input voltage Needed to start up 3.7 V
Once Operating 3 V
VIN_OP_H Minimum voltage hysteresis 1 V
IQ Non-switching input current; measured at VIN pin (3) VIN =13.5 V, VFB = +5%, VBIAS = 5 V 0.662 10 µA
ISD Shutdown quiescent current; measured at VIN pin VEN = 0 V, VIN = 13.5V 0.662 7.5 µA
IB Current into BIAS pin (not switching) VIN = 13.5 V, VFB = +5%, VBIAS = 5 V, Auto Mode Enabled  18.5 26 µA
ENABLE (EN PIN)
VEN Enable input-threshold voltage - rising VEN rising 1.161 1.263 1.365 V
VEN_HYST Enable threshold hysteresis 0.25 0.5 V
VEN_WAKE Enable Wake-up threshold 0.4 V
IEN Enable pin input current VIN = VEN = 13.5 V 0.3 50 nA
INTERNAL LDO (VCC PIN)
VCC Internal VCC voltage VIN = 13.5 V, VBIAS = 0V 3.4 V
VIN = 13.5 V, VBIAS = 3.3 V, 20 mA 3.2
VCC_UVLO VIN voltage at which Internal VCC under voltage lock-out is released IVCC = 0A 3.7 V
VCC_UVLO_HYST Internal VCC under voltage lock-out hysteresis Hysteresis below VCC_UVLO 1.2 V
VOLTAGE REFERENCE (FB PIN)
VFB_3.3V Initial reference voltage accuracy for 3.3 V option VIN = 5 V to 36 V, FPWM Mode 3.24 3.3 3.34 V
VFB_4V Initial reference voltage accuracy for 4 V option
VIN = 5 V to 36 V, FPWM Mode

 3.9 4 4.04
VFB_5V Initial reference voltage accuracy for 5 V option VIN = 6 V to 36 V, FPWM Mode 4.91 5 5.06 V
VFB Initial reference voltage accuracy for adjustable (1 V FB) versions VIN = 3.0 V to 36 V, FPWM Mode 0.99 1 1.01 V
RFB Resistance from FB to AGND 5 V Fixed Option 1.8 MΩ

4 V Fixed Option

 2.1
3.3 V Fixed Option 2.2
IFB Input current from FB to AGND Adjustable versions only, VFB = 1 V 50 nA
CURRENT LIMITS
ISC_6 Short circuit high-side current Limit 6 A Variant, Duty cycle approaches 0% 8 10.35 12.6 A
ILS-LIMIT_6 Low-side current limit 5.7 6.9 8.1 A
IPEAK-MIN_6 Minimum Peak Inductor Current 1.2 A
IL-NEG_6 Negative current limit –4.9 –3.8 –2.4 A
ISC_8 Short circuit high-side current Limit 8 A Variant, Duty cycle approaches 0% 11.5 13.8 15.6 A
ILS-LIMIT_8 Low-side current limit 8 9.2 10.4 A
IPEAK-MIN_8 Minimum Peak Inductor Current 1.6 A
IL-NEG_8 Negative current limit –6.4 –5.3 –3.9 A
ISC_10 Short circuit high-side current Limit 10 A Variant, Duty cycle approaches 0% 14 17.3 20 A
ILS-LIMIT_10 Low-side current limit 9.8 11.5 12.9 A
IPEAK-MIN_10 Minimum Peak Inductor Current 1.8 A
IL-NEG_10 Negative current limit –6.6 –5.3 –4 A
IL-ZC Zero-cross current limit. Positive current direction is out of SW pin. Auto Mode, static measurement 10 200 mA
VHICCUP Hiccup threshold on FB pin 0.36 0.4 0.44 V
POWER GOOD (/RESET PIN)
V  RESET-OV RESET upper threshold - Rising % of FB voltage 110 112 114 %
V  RESET-UV RESET lower threshold - Falling % of FB voltage 92 94 96.5 %
V  RESET_GUARD RESET UV threshold as percentage of steady state output voltage with output voltage and UV threshold, falling, read at the same TJ, and VIN. Falling 97 %
V  RESET-HYS-FALLING RESET fallling threshold hysteresis % of FB voltage 0.5 1.3 2.5 %
V  RESET-HYS-RISING RESET rising threshold hysteresis % of FB voltage 0.5 1.3 2.5 %
V  RESET_VALID Minimum input voltage for proper RESET function Measured when V RESET  < 0.4 V with 10 kOhm pullup to external 5 V 1.2 V
VOL RESET Low-level function output voltage 46.0 µA pull up to RESET pin, VIN = 1.0 V, VEN = 0 V 0.4 V
1 mA pull up to RESET pin, VIN = 13.5 V, VEN = 0 V 0.4
2 mA pull up to RESET pin, VIN = 13.5 V, VEN = 3.3 V 0.4
R RESET RESET ON resistance, VEN = 5 V, 1mA pull up current 44 125 Ω
R RESET RESET ON resistance, VEN = 0 V, 1mA pull up current 18 40 Ω
OSCILLATOR (SYNC/MODE PIN)
VSYNCDL SYNC/MODE input voltage low 0.4 V
VSYNCDH SYNC/MODE input voltage high 1.7 V
VSYNCD_HYST SYNC/MODE input voltage hysteresis 0.185 1 V
RSYNC Internal pulldown resistor to ensure SYNC/MODE doesn't float 100 kΩ
HIGH SIDE DRIVE (CBOOT PIN)
VCBOOT_UVLO Voltage on CBOOT pin compared to SW which will turnoff high-side switch 1.9 V
MOSFETS
RDS-ON-HS High-side MOSFET on-resistance Load = 1 A, CBOOT-SW = 3.2 V 21 39 mΩ
RDS-ON-LS Low-side MOSFET on-resistance Load = 1 A, CBOOT-SW = 3.2 V 13 25 mΩ