JAJS854E May   1999  – December 2024 LM6172

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics ±15V
    6. 5.6 Electrical Characteristics ±5V
    7. 5.7 Typical Characteristics: D (SOIC, 8) Package
    8. 5.8 Typical Characteristics: P (PDIP, 8) Package
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Slew Rate
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Circuit Operation
      2. 7.1.2 Reduce Settling Time
      3. 7.1.3 Drive Capacitive Loads
      4. 7.1.4 Compensation for Input Capacitance
      5. 7.1.5 Termination
    2. 7.2 Typical Application
      1. 7.2.1 Application Circuits
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power Supply Bypassing
      2. 7.3.2 Power Dissipation
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Printed Circuit Boards and High-Speed Op Amps
        2. 7.4.1.2 Using Probes
        3. 7.4.1.3 Components Selection and Feedback Resistor
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1.1 Circuit Operation

The class AB input stage in LM6172 is fully symmetrical and has a similar slewing characteristic to the current feedback amplifiers. In the functional block diagram of Section 6.2, Q1 through Q4 form the equivalent of the current feedback input buffer, RE the equivalent of the feedback resistor, and stage A buffers the inverting input. The triple-buffered output stage isolates the gain stage from the load to provide low output impedance.