SNOS792E May   1999  – December 2024 LM6172

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics ±15V
    6. 5.6 Electrical Characteristics ±5V
    7. 5.7 Typical Characteristics: D (SOIC, 8) Package
    8. 5.8 Typical Characteristics: P (PDIP, 8) Package
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Slew Rate
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Circuit Operation
      2. 7.1.2 Reduce Settling Time
      3. 7.1.3 Drive Capacitive Loads
      4. 7.1.4 Compensation for Input Capacitance
      5. 7.1.5 Termination
    2. 7.2 Typical Application
      1. 7.2.1 Application Circuits
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power Supply Bypassing
      2. 7.3.2 Power Dissipation
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Printed Circuit Boards and High-Speed Op Amps
        2. 7.4.1.2 Using Probes
        3. 7.4.1.3 Components Selection and Feedback Resistor
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
  • P|8
サーマルパッド・メカニカル・データ

5.4 Thermal Information

THERMAL METRIC(1) LM6172 UNIT
D (SOIC) P (PDIP)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 172 108 ℃/W
RθJC(top) Junction-to-case (top) thermal resistance 62.4 52.4 ℃/W
RθJB Junction-to-board thermal resistance 55.7 51.9 ℃/W
ΨJT Junction-to-top characterization parameter 16.5 6.8 ℃/W
ΨJB Junction-to-board characterization parameter 55.1 51.1 ℃/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A ℃/W
(1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.