JAJSIW6E March   2020  – April 2022 LM62440-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Characteristics
    7. 8.7 Systems Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  EN Uses for Enable and VIN UVLO
      2. 9.3.2  MODE/SYNC Pin Operation
        1. 9.3.2.1 Level-Dependent MODE/SYNC Pin Control
        2. 9.3.2.2 Pulse-Dependent MODE/SYNC Pin Control
        3. 9.3.2.3 Clock Locking
      3. 9.3.3  PGOOD Output Operation
      4. 9.3.4  Internal LDO, VCC UVLO, and BIAS Input
      5. 9.3.5  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
      6. 9.3.6  Adjustable SW Node Slew Rate
      7. 9.3.7  Spread Spectrum
      8. 9.3.8  Soft Start and Recovery From Dropout
      9. 9.3.9  Output Voltage Setting
      10. 9.3.10 Overcurrent and Short Circuit Protection
      11. 9.3.11 Thermal Shutdown
      12. 9.3.12 Input Supply Current
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Active Mode
        1. 9.4.3.1 CCM Mode
        2. 9.4.3.2 Auto Mode – Light-Load Operation
          1. 9.4.3.2.1 Diode Emulation
          2. 9.4.3.2.2 Frequency Reduction
        3. 9.4.3.3 FPWM Mode – Light-Load Operation
        4. 9.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 9.4.3.5 Dropout
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Choosing the Switching Frequency
        2. 10.2.2.2  Setting the Output Voltage
        3. 10.2.2.3  Inductor Selection
        4. 10.2.2.4  Output Capacitor Selection
        5. 10.2.2.5  Input Capacitor Selection
        6. 10.2.2.6  BOOT Capacitor
        7. 10.2.2.7  BOOT Resistor
        8. 10.2.2.8  VCC
        9. 10.2.2.9  BIAS
        10. 10.2.2.10 CFF and RFF Selection
        11. 10.2.2.11 External UVLO
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Ground and Thermal Considerations
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.2.2 Pulse-Dependent MODE/SYNC Pin Control

Most systems that require more than a single mode of operation from the LM62440-Q1 are controlled by digital circuitry such as a microprocessor. These systems can generate dynamic signals easily but have difficulty generating multi-level signals. Pulse-Dependent MODE/SYNC pin control is useful with these systems.

To initiate Pulse-Dependent MODE/SYNC pin control, a valid sync signal must be applied. Upon completion of the fourth pulse in a valid synchronization pulse train, the SYNC mode pin operates in Pulse-Dependent MODE/SYNC control mode, shown in Figure 9-3 and Figure 9-4. The only way to return to Level-Dependent MODE/SYNC control is to restart the LM62440-Q1.

GUID-9CADD277-C687-4B28-96C4-511764229E52-low.gif Figure 9-3 Transition from FPWM Mode to Pulse-Dependent Control
GUID-805DCDB6-3A51-4145-8249-5592F70C349F-low.gif Figure 9-4 Transition from Auto Mode to Pulse-Dependent Control

Once Pulse-Dependent MODE/SYNC control has been initiated, Table 9-2 shows a summary of the pulse dependent mode selection settings.

Table 9-2 Pulse-Dependent Mode Selection Settings
MODE/SYNC Input Mode
> VMODE_H FPWM with spread spectrum
< VMODE_L Auto mode with spread spectrum
Synchronization Clock SYNC mode without spread spectrum
> VMODE_H AND Double Pulse (Figure 9-6) FPWM without spread spectrum
< VMODE_L AND Double Pulse (Figure 9-7) Auto mode without spread spectrum

Figure 9-5 shows the transition between auto mode and FPWM mode while in Pulse-Dependent MODE/SYNC control. The LM62440-Q1 transitions to a new mode of operation after the time, tMODE.

GUID-32E80C25-CC68-4F3C-83BE-CA4E6365186B-low.gif Figure 9-5 Transition from Auto Mode and FPWM Mode

Two positive going pulses can be used to turn off spread spectrum in auto and FPWM modes. The two positive pulses must be consistent with the characteristics of a valid sync signal. Figure 9-6 through Figure 9-9 show the only waveforms that result in spread spectrum being turned off. Refer to the Electrical Characteristics for more information about the timing specifications.

GUID-2752703F-6F06-49A5-A521-8FB79C9618FF-low.gif Figure 9-6 Spread Spectrum Disabled in FPWM Mode
GUID-4BD3D4CA-BA23-4267-8B49-4F241326EF46-low.gif Figure 9-7 Spread Spectrum Disabled in Auto Mode
GUID-02BD2376-2170-42E5-ADD5-5A1024A14B33-low.gif Figure 9-8 Spread Spectrum Disabled in Transition from FPWM Mode to Auto Mode
GUID-7612026C-A2F6-4FEB-9677-2D0E1D73F972-low.gif Figure 9-9 Spread Spectrum Disabled in Transition from Auto Mode to FPWM Mode

To enter the SYNC mode, the valid synchronization signal must be present for 2048 cycles.

If MODE/SYNC voltage becomes constant longer than tMODE, the LM62440-Q1 enters either auto mode or FPWM mode. At this time, spread spectrum is turned on and MODE/SYNC operates in Pulse-Dependent mode.

GUID-649CE5C6-E3CF-4408-8F9F-0C85C3E4B7BF-low.gif Figure 9-10 Transition from SYNC Mode to Auto Mode
GUID-6E43A49E-F1B0-40A5-9308-C53F7AC87DF0-low.gif Figure 9-11 Transition from SYNC Mode to FPWM Mode