JAJSJT2D February   2020  – August 2021 LM61480-Q1 , LM61495-Q1 , LM62460-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 System Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Output Voltage Selection
      2. 8.3.2  Enable EN Pin and Use as VIN UVLO
      3. 8.3.3  SYNC/MODE Uses for Synchronization
      4. 8.3.4  Clock Locking
      5. 8.3.5  Adjustable Switching Frequency
      6. 8.3.6  RESET Output Operation
      7. 8.3.7  Internal LDO, VCC UVLO, and BIAS Input
      8. 8.3.8  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
      9. 8.3.9  Adjustable SW Node Slew Rate
      10. 8.3.10 Spread Spectrum
      11. 8.3.11 Soft Start and Recovery From Dropout
      12. 8.3.12 Overcurrent and Short Circuit Protection
      13. 8.3.13 Hiccup
      14. 8.3.14 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 Peak Current Mode Operation
        2. 8.4.3.2 Auto Mode Operation
          1. 8.4.3.2.1 Diode Emulation
        3. 8.4.3.3 FPWM Mode Operation
        4. 8.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
        6. 8.4.3.6 Recovery from Dropout
        7. 8.4.3.7 Other Fault Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Choosing the Switching Frequency
        2. 9.2.2.2  Setting the Output Voltage
        3. 9.2.2.3  Inductor Selection
        4. 9.2.2.4  Output Capacitor Selection
        5. 9.2.2.5  Input Capacitor Selection
        6. 9.2.2.6  BOOT Capacitor
        7. 9.2.2.7  BOOT Resistor
        8. 9.2.2.8  VCC
        9. 9.2.2.9  CFF and RFF Selection
        10. 9.2.2.10 RSPSP Selection
        11. 9.2.2.11 RT Selection
        12. 9.2.2.12 RMODE Selection
        13. 9.2.2.13 External UVLO
        14. 9.2.2.14 Maximum Ambient Temperature
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground and Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Glossary
    6. 12.6 Electrostatic Discharge Caution
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Power Supply Recommendations

The characteristics of the input supply must be capable of delivering the required input current to the loaded regulator. The average input current can be estimated with Equation 9.

Equation 9. GUID-FFDA2A2C-2325-4BE3-846E-EA407DBA9673-low.gif

where

  • η is the efficiency

If the regulator is connected to the input supply through long wires or PCB traces, special care is required to achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR ceramic input capacitors, can form an underdamped resonant circuit. This can result in overvoltage transients at the input to the regulator or tripping UVLO. Consider that the supply voltage can dip when a load transient is applied to the output depending on the parasitic resistance and inductance of the harness and characteristics of the supply. If the application is operating close to the minimum input voltage, this dip can cause the regulator to momentarily shut down and reset. The best way to solve these kinds of issues is to reduce the distance from the input supply to the regulator. Additionally, use an aluminum input capacitor in parallel with the ceramics. The moderate ESR of this type of capacitor helps damp the input resonant circuit and reduce any overshoots or undershoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and help hold the input voltage steady during large load transients.

In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device has a snap-back characteristic (thyristor type). It is not recommended to use a device with this type of characteristic. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the output voltage of the regulator, the output capacitors discharge through the device back to the input. This uncontrolled current flow can damage the device.

The input voltage must not be allowed to fall below the output voltage. In this scenario, such as a shorted input test, the output capacitors discharge through the internal parasitic diode found between the VIN and SW pins of the device. During this condition, the current can become uncontrolled, possibly causing damage to the device. If this scenario is considered likely, then use a Schottky diode between the input supply and the output.