JAJSMA0A July   2020  – July 2021 LM63610-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 System Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Sync/Mode Selection
      2. 8.3.2 Output Voltage Selection
      3. 8.3.3 Switching Frequency Selection
        1. 8.3.3.1 Spread Spectrum Option
      4. 8.3.4 Enable and Start-up
      5. 8.3.5 RESET Flag Output
      6. 8.3.6 Undervoltage Lockout and Thermal Shutdown and Output Discharge
    4. 8.4 Device Functional Modes
      1. 8.4.1 Overview
      2. 8.4.2 Light Load Operation
        1. 8.4.2.1 Sync/FPWM Operation
      3. 8.4.3 Dropout Operation
      4. 8.4.4 Minimum On-time Operation
      5. 8.4.5 Current Limit and Short-Circuit Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Choosing the Switching Frequency
        2. 9.2.2.2 Setting the Output Voltage
          1. 9.2.2.2.1 CFF Selection
        3. 9.2.2.3 Inductor Selection
        4. 9.2.2.4 Output Capacitor Selection
        5. 9.2.2.5 Input Capacitor Selection
        6. 9.2.2.6 CBOOT
        7. 9.2.2.7 VCC
        8. 9.2.2.8 External UVLO
        9. 9.2.2.9 Maximum Ambient Temperature
      3. 9.2.3 Application Curves
      4. 9.2.4 EMI Performance Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground and Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.5 RESET Flag Output

The RESET flag function (RESET output pin) of the LM63610-Q1 devices can be used to reset a system microprocessor whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation for short excursions of the output voltage, such as during line and load transients. Output voltage excursions lasting less than tdg do not trip the RESET flag. Once the FB voltage has returned to the regulation value and after a delay of trise-delay, the RESET flag goes high. RESET operation can best be understood by reference to Figure 8-3 and Figure 8-4.

The RESET output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic supply. It can also be pulled up to either VCC or VOUT through an appropriate resistor, as desired. Values of pullup resistor in the range of 10 kΩ to 100 kΩ are reasonable. If this function is not needed, the RESET pin can be left floating. When EN is pulled low, the flag output is also forced low. With EN low, RESET remains valid as long as the input voltage is ≥ 1.2 V (typical). Limit the current into the RESET flag pin to about 5 mA D.C. The maximum current is internally limited to about 50 mA when the device is enabled and about 65 mA when the device is disabled. The internal current limit protects the device from any transient currents that can occur when discharging a filter capacitor connected to this output.

GUID-F9B07725-25BA-469A-A008-C4FA5759F392-low.gifFigure 8-3 Static RESET Operation
GUID-283EA88E-DD78-4152-999D-8316B71DF330-low.gifFigure 8-4 RESET Timing Behavior