JAJSJO5B October 2022 – August 2024 LM64440-Q1 , LM64460-Q1
PRODUCTION DATA
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CBOOT | 1 | P | High-side driver supply rail. Connect a 100nF capacitor between SW and CBOOT. An internal bootstrap diode connects to VCC and allows the bootstrap capacitor to charge when SW is low. |
NC | 2 | — | No internal connection |
BIAS | 3 | P | Input to the internal LDO. Connect to the output voltage point to improve efficiency. Connect an optional high-quality 0.1µF to 1µF capacitor from this pin to GND for improved noise immunity. If the output voltage is above 12V, connect BIAS to GND. |
VCC | 4 | O | Internal LDO output. VCC supplies the internal control circuits. Do not connect to any external loads. Connect a high-quality 1µF capacitor from VCC to GND. |
FB | 5 | I | Output voltage feedback input to the internal control loop. Connect to the output voltage sense point for fixed 3.3V or 5V output voltage settings. Connect to a feedback divider tap point to set an adjustable output voltage. Do not float or connect to GND. |
PGOOD | 6 | O | Open-drain power-good status indicator output. Pull up PGOOD to a suitable voltage supply through a current-limiting resistor. High = power OK, low = fault. The PGOOD output goes low when EN = low, VIN > 1V. |
MODE/SYNC | 7 | I | MODE/SYNC controls the mode of operation of the LM64460-Q1. Modes include AUTO mode (automatic PFM / PWM operation), FPWM, and synchronization to an external clock. When synchronized, the clock triggers on rising edge of an external clock signal. Spread spectrum operation is also controlled by this pin. See MODE/SYNC Operation. Do not float this pin. |
EN | 8 | I | Enable input and undervoltage lockout (UVLO) programming pin. If the EN voltage is below 0.4V, the converter is in shutdown mode with all functions disabled. If the EN voltage is greater than 1.263V (and the VCC voltage is above the UVLO threshold), the converter is active and switching. Use the precision enable function to set an adjustable input voltage UVLO with hysteresis. See Precision Enable and Input Voltage UVLO (EN). |
NC | 9 | — | No internal connection |
VIN2 | 10 | P | Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin to PGND2. A low-impedance connection must be provided to VIN1. |
NC | 11 | — | No internal connection |
PGND2 | 12 | G | Power-ground connection to the internal low-side MOSFET. Connect to system ground. A low-impedance connection must be provided to PGND1. Connect a high-quality bypass capacitor or capacitors from this pin to VIN2. |
NC | 13 | — | No internal connection |
SW1 | 14 | P | Switch node of the converter. Connect to the output inductor. |
SW2 | 15 | ||
SW3 | 16 | ||
NC | 17 | — | No internal connection |
PGND1 | 18 | G | Power ground to the internal low-side MOSFET. Connect to system ground. A low-impedance connection must be provided to PGND2. Connect a high-quality bypass capacitor or capacitors from this pin to VIN1. |
NC | 19 | — | No internal connection |
VIN1 | 20 | P | Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin to PGND1. A low-impedance connection must be provided to VIN2. |
NC | 21 | — | No internal connection |
SW4 | 22 | P | Switch node of the converter. Connect to the bootstrap capacitor. |
GND | – | G | Exposed pad of the package internally connected to ground. The exposed pad must be connected to the PCB inner-layer system ground plane or planes using numerous thermal vias to reduce thermal impedance. See Layout Guidelines. |