JAJSJO5B October   2022  – August 2024 LM64440-Q1 , LM64460-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Wettable Flanks
    2. 5.2 Pinout Design for Clearance and FMEA
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Systems Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN1, VIN2)
      2. 7.3.2  Output Voltage Setpoint (FB)
      3. 7.3.3  Precision Enable and Input Voltage UVLO (EN)
      4. 7.3.4  MODE/SYNC Operation
        1. 7.3.4.1 Level-Dependent MODE/SYNC Control
        2. 7.3.4.2 Pulse-Dependent MODE/SYNC Control
      5. 7.3.5  Clock Locking
      6. 7.3.6  Power-Good Monitor (PGOOD)
      7. 7.3.7  Bias Supply Regulator (VCC, BIAS)
      8. 7.3.8  Bootstrap Voltage and UVLO (CBOOT)
      9. 7.3.9  Spread Spectrum
      10. 7.3.10 Soft Start and Recovery From Dropout
      11. 7.3.11 Overcurrent and Short-Circuit Protection
      12. 7.3.12 Thermal Shutdown
      13. 7.3.13 Input Supply Current
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 AUTO Mode – Light-Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Foldback
        3. 7.4.3.3 FPWM Mode – Light-Load Operation
        4. 7.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – Automotive Synchronous 6A Buck Regulator at 2.1MHz
        1. 8.2.1.1 Design Requirements
      2. 8.2.2 Design 2 – Automotive Synchronous 4A Buck Regulator at 2.1MHz
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.2.2.2  Setting the Output Voltage
          3. 8.2.2.2.3  Choosing the Switching Frequency
          4. 8.2.2.2.4  Inductor Selection
          5. 8.2.2.2.5  Output Capacitor Selection
          6. 8.2.2.2.6  Input Capacitor Selection
          7. 8.2.2.2.7  Bootstrap Capacitor
          8. 8.2.2.2.8  VCC Capacitor
          9. 8.2.2.2.9  BIAS Power Connection
          10. 8.2.2.2.10 Feedforward Network
          11. 8.2.2.2.11 Input Voltage UVLO
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Design and Layout
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.4 Thermal Information

The value of RθJA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD 51-7 and simulated on a 4-layer JEDEC board. They do not represent the performance obtained in an actual application. For example, the EVM for this device achieves an RθJA of 23.5℃/W. 
THERMAL METRIC(1) LM64460-Q1, LM64440-Q1 UNIT
RYF (VQFN)
22 PINS
RθJA Junction-to-ambient thermal resistance (LM64460-Q1 EVM)(3) 23.5 °C/W
RθJA Junction-to-ambient thermal resistance (JESD 51-7)(2) 38.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance    30.3 °C/W
RθJB Junction-to-board thermal resistance 8.8 °C/W
ΨJT Junction-to-top characterization parameter 1 °C/W
ΨJB Junction-to-board characterization parameter 8.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The value of RθJA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD 51-7 and simulated on a 4-layer JEDEC board. They do not represent the performance obtained in an actual application.
(3) Refer to the LM64460-Q1 EVM User's Guide for board layout and additional information. For thermal design information please see the Application Information section.