JAJSJO5B October 2022 – August 2024 LM64440-Q1 , LM64460-Q1
PRODUCTION DATA
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LM644x0-Q1 は、非常に優れた効率と非常に低い IQ を備えた車載用同期整流降圧 DC/DC コンバータのファミリに属しています。ハイサイドおよびローサイド MOSFET を内蔵しているため、3V~36V という広い入力電圧範囲にわたって最大 6A の出力電流が供給されます。42V までの負荷ダンプ過渡に対応しており、。このコンバータは、ドロップアウトからのソフト回復を実装しているため、出力のオーバーシュートを除去できます。
LM644x0-Q1 は、さまざまな機能を搭載することにより非常に優れた EMI 特性を実現しています。その機能の例としては、スペクトラム拡散周波数変調、スイッチ ノードのリンギングを緩和する低 EMI の Enhanced HotRod QFN パッケージ、理想的な入力コンデンサ配置に適した対称型ピン配置があります。アプリケーション特有の要件に基づいて効率や設計サイズを最適化すると同時に、ノイズの影響を受けやすい周波数帯を避けるため、スイッチング周波数は 200kHz~2.2MHz の範囲で同期可能です。
PFM モードでは、軽負荷動作時の周波数フォールドバックが可能であり、わずか 7µA (標準値) の無負荷時消費電流、および軽負荷時の効率向上を実現できます。PWM モードと PFM モードの間のシームレスな移行、小さな MOSFET オン抵抗、外部バイアス入力により、負荷範囲全体にわたって非常に優れた効率および熱性能が得られます。パッケージには、重要な電源ピンの間に複数の NC ピンが配置されており、これによって故障モード影響解析 (FMEA) の結果が改善されます。
DEVICE | ORDERABLE PART NUMBER | OUTPUT VOLTAGE | CURRENT | SPREAD SPECTRUM | LIGHT-LOAD MODE | SWITCHING FREQUENCY | TEST TEMPERATURES |
---|---|---|---|---|---|---|---|
LM64460-Q1 | LM64460APPQRYFRQ1 | Adjustable | 6A | Pin selectable | Pin selectable | 2.1MHz | Standard |
LM64460APPSRYFRQ1 | Adjustable | 6A | Pin selectable | Pin selectable | 2.1MHz | Tri-temperature | |
LM64460BPPQRYFRQ1 | 3.3V | 6A | Pin selectable | Pin selectable | 2.1MHz | Standard | |
LM64460CPPQRYFRQ1 | 5V | 6A | Pin selectable | Pin selectable | 2.1MHz | Standard | |
LM63460-Q1 | LM63460AASQRYFRQ1 | Adjustable | 6A | On | AUTO | Adjustable | Standard |
LM63460AFSQRYFRQ1 | Adjustable | 6A | On | FPWM | Adjustable | Standard | |
LM64440-Q1 | LM64440APPQRYFRQ1 | Adjustable | 4A | Pin selectable | Pin selectable | 2.1MHz | Standard |
LM64440BPPQRYFRQ1 | 3.3V | 4A | Pin selectable | Pin selectable | 2.1MHz | Standard | |
LM64440CPPQRYFRQ1 | 5V | 4A | Pin selectable | Pin selectable | 2.1MHz | Standard | |
LM63440-Q1 | LM63440AASQRYFRQ1 | Adjustable | 4A | On | AUTO | Adjustable | Standard |
LM63440AFSQRYFRQ1 | Adjustable | 4A | On | FPWM | Adjustable | Standard |
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CBOOT | 1 | P | High-side driver supply rail. Connect a 100nF capacitor between SW and CBOOT. An internal bootstrap diode connects to VCC and allows the bootstrap capacitor to charge when SW is low. |
NC | 2 | — | No internal connection |
BIAS | 3 | P | Input to the internal LDO. Connect to the output voltage point to improve efficiency. Connect an optional high-quality 0.1µF to 1µF capacitor from this pin to GND for improved noise immunity. If the output voltage is above 12V, connect BIAS to GND. |
VCC | 4 | O | Internal LDO output. VCC supplies the internal control circuits. Do not connect to any external loads. Connect a high-quality 1µF capacitor from VCC to GND. |
FB | 5 | I | Output voltage feedback input to the internal control loop. Connect to the output voltage sense point for fixed 3.3V or 5V output voltage settings. Connect to a feedback divider tap point to set an adjustable output voltage. Do not float or connect to GND. |
PGOOD | 6 | O | Open-drain power-good status indicator output. Pull up PGOOD to a suitable voltage supply through a current-limiting resistor. High = power OK, low = fault. The PGOOD output goes low when EN = low, VIN > 1V. |
MODE/SYNC | 7 | I | MODE/SYNC controls the mode of operation of the LM64460-Q1. Modes include AUTO mode (automatic PFM / PWM operation), FPWM, and synchronization to an external clock. When synchronized, the clock triggers on rising edge of an external clock signal. Spread spectrum operation is also controlled by this pin. See MODE/SYNC Operation. Do not float this pin. |
EN | 8 | I | Enable input and undervoltage lockout (UVLO) programming pin. If the EN voltage is below 0.4V, the converter is in shutdown mode with all functions disabled. If the EN voltage is greater than 1.263V (and the VCC voltage is above the UVLO threshold), the converter is active and switching. Use the precision enable function to set an adjustable input voltage UVLO with hysteresis. See Precision Enable and Input Voltage UVLO (EN). |
NC | 9 | — | No internal connection |
VIN2 | 10 | P | Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin to PGND2. A low-impedance connection must be provided to VIN1. |
NC | 11 | — | No internal connection |
PGND2 | 12 | G | Power-ground connection to the internal low-side MOSFET. Connect to system ground. A low-impedance connection must be provided to PGND1. Connect a high-quality bypass capacitor or capacitors from this pin to VIN2. |
NC | 13 | — | No internal connection |
SW1 | 14 | P | Switch node of the converter. Connect to the output inductor. |
SW2 | 15 | ||
SW3 | 16 | ||
NC | 17 | — | No internal connection |
PGND1 | 18 | G | Power ground to the internal low-side MOSFET. Connect to system ground. A low-impedance connection must be provided to PGND2. Connect a high-quality bypass capacitor or capacitors from this pin to VIN1. |
NC | 19 | — | No internal connection |
VIN1 | 20 | P | Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin to PGND1. A low-impedance connection must be provided to VIN2. |
NC | 21 | — | No internal connection |
SW4 | 22 | P | Switch node of the converter. Connect to the bootstrap capacitor. |
GND | – | G | Exposed pad of the package internally connected to ground. The exposed pad must be connected to the PCB inner-layer system ground plane or planes using numerous thermal vias to reduce thermal impedance. See Layout Guidelines. |
100% automated visual inspection (AVI) post-assembly is typically required to meet requirements for high reliability and robustness. Standard quad-flat no-lead (VQFN) packages do not have solderable or exposed pins and terminals that are easily viewed. Therefore, visually determining whether or not the package is successfully soldered onto the printed-circuit board (PCB) is difficult. The wettable-flank process was developed to resolve the issue of side-lead wetting of leadless packaging. The LM644x0-Q1 is assembled using a 22-pin Enhanced HotRod QFN package with wettable flanks to provide a visual indicator of solderability, which reduces the inspection time and manufacturing costs.
The LM644x0-Q1 has a carefully designed pinout arrangement that provides additional clearance spacing between high-voltage pins (VIN, SW, and CBOOT) and nearby low-voltage pins (such as PGND). Moreover, the LM644x0-Q1 pinout is designed for critical automotive applications requiring functional safety system design with stricter reliability and higher durability. In terms of pin FMEA (failure mode effects analysis), the typical failure scenarios considered include short circuit to ground, short circuit to input supply (VIN), short circuit to a neighboring pin, and if a pin is left open circuit. These faults are considered as applied externally to the IC and therefore are board-level failures rather than IC-level reliability failures. Example sources of such faults are stray conductive filaments causing pin-to-pin shorts or a board manufacturing defect causing an open-circuit track. The LM644x0-Q1 fixed output voltage versions in particular are considered pin-FMEA compliant in the event of a pin short circuit to a neighboring pin, so the output voltage stays at or below the regulation voltage.