JAJSJO5A October   2022  – October 2023 LM64460-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1. 6.1 Wettable Flanks
    2. 6.2 Pinout Design for Clearance and FMEA
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Systems Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN1, VIN2)
      2. 8.3.2  Output Voltage Setpoint (FB)
      3. 8.3.3  Precision Enable and Input Voltage UVLO (EN)
      4. 8.3.4  MODE/SYNC Operation
        1. 8.3.4.1 Level-Dependent MODE/SYNC Control
        2. 8.3.4.2 Pulse-Dependent MODE/SYNC Control
      5. 8.3.5  Clock Locking
      6. 8.3.6  Power-Good Monitor (PGOOD)
      7. 8.3.7  Bias Supply Regulator (VCC, BIAS)
      8. 8.3.8  Bootstrap Voltage and UVLO (CBOOT)
      9. 8.3.9  Spread Spectrum
      10. 8.3.10 Soft Start and Recovery From Dropout
      11. 8.3.11 Overcurrent and Short-Circuit Protection
      12. 8.3.12 Thermal Shutdown
      13. 8.3.13 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 CCM Mode
        2. 8.4.3.2 AUTO Mode – Light-Load Operation
          1. 8.4.3.2.1 Diode Emulation
          2. 8.4.3.2.2 Frequency Foldback
        3. 8.4.3.3 FPWM Mode – Light-Load Operation
        4. 8.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – Automotive Synchronous Buck Regulator at 2.1 MHz
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2  Setting the Output Voltage
          3. 9.2.1.2.3  Choosing the Switching Frequency
          4. 9.2.1.2.4  Inductor Selection
          5. 9.2.1.2.5  Output Capacitor Selection
          6. 9.2.1.2.6  Input Capacitor Selection
          7. 9.2.1.2.7  Bootstrap Capacitor
          8. 9.2.1.2.8  VCC Capacitor
          9. 9.2.1.2.9  BIAS Power Connection
          10. 9.2.1.2.10 Feedforward Network
          11. 9.2.1.2.11 Input Voltage UVLO
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Thermal Design and Layout
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 13.5 V.  VIN1 shorted to VIN2 = VIN.  VOUT is the converter output voltage.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE AND CURRENT
VIN_OPERATE Input operating voltage(1) Needed to start up 3.95 V
Once operating 3.0
VIN_OPERATE_H Hysteresis(1) 1 V
IQ_VIN Operating quiescent current (not switching)(2) VFB = +5%, VBIAS = 5 V, VOUT = 5 V 9 18 µA
IQ Operating quiescent current (not switching); measured at VIN pin(3) VFB = +5%, VBIAS = 5 V 0.6 6 µA
IBIAS Current into BIAS pin (not switching, maximum at TJ = 125°C)(3) VFB = +5%, VBIAS = 5 V, AUTO mode 24 31.2 µA
ISD Shutdown quiescent current; measured at VIN pin VEN = 0 V, TJ = 25°C 0.6 6 µA
ENABLE
VEN-TH Enable input threshold voltage (rising) 1.263 V
VEN-ACC Enable input threshold voltage – rising deviation from typical –5% 5%
VEN-HYST Enable threshold hysteresis as percentage of VEN-TH (typical) 24% 28% 32%
VEN-WAKE Enable wake-up threshold 0.4 V
IEN Enable pin input current VIN = VEN = 13.5 V 2.3 nA
LDO AND VCC
VCC Internal VCC voltage VBIAS > 3.4  V, CCM operation(1) 3.3 V
VBIAS = 3.1 V, non-switching 3.1
VCC-UVLO Internal VCC undervoltage lockout VCC rising undervoltage threshold 3.6 V
VCC-UVLO-HYST Internal VCC undervoltage lockout hysteresis Hysteresis below VCC-UVLO 1.1 V
FEEDBACK
VFB_acc Initial reference voltage accuracy for 5-V, 3.3-V and adjustable output versions VIN = 3.3 V to 36 V, TJ = 25°C, FPWM mode –1% 1%
VOUT_acc Reference voltage accuracy for fixed 3.3-V VOUT trim option FPWM mode 3.2587 3.3 3.3413 V
VOUT_acc Reference voltage accuracy for fixed 5-V VOUT trim option FPWM mode 4.9375 5 5.0625 V
RFB Resistance from FB to GND 5-V option 1.85 MΩ
3.3-V option 2.1
IFB Input current from FB to GND  Adjustable versions only, VFB = 1 V 1 50 nA
OSCILLATOR
fSW Switching frequency Center frequency with or without spread spectrum, CCM operation 1.9 2.1 2.3 MHz
fS_SS Frequency span of spread spectrum operation – largest deviation from center frequency Spread spectrum active 2%
fPSS Spread spectrum pattern frequency(1) Spread spectrum active, fSW = 2.1 MHz 1.5 Hz
MODE/SYNC
IMODE/SYNC MODE/SYNC pin leakage current after startup VMODE/SYNC = 3.3 V 1 nA
VMODE/SYNC = 5.5 V 1
VMODE_L MODE/SYNC input voltage low 0.4 V
VMODE_H MODE/SYNC input voltage high 1.6 V
VSYNCD_HYST MODE/SYNC input voltage hysteresis 0.155 1 V
VMODE_H2 Spread spectrum on if MODE/SYNC voltage is below this voltage and above VSYNCDH Level-dependent operation 2.5 V
VMODE_H3 Spread spectrum off if MODE/SYNC is above this voltage
Level-dependent operation

 4.9 V
RMODE_H MODE/SYNC attached resistance indicating spread spectrum off
Level-dependent operation

 30 kΩ
RMODE_L MODE/SYNC attached resistance indicating spread spectrum on
Level-dependent operation

 6 kΩ
MOSFETS
RDS(on)HS Power switch on-resistance High-side MOSFET RDS(on) 41 82 mΩ
RDS(on)LS Power switch on-resistance Low-side MOSFET RDS(on) 21 45 mΩ
VBOOT-UVLO Voltage on CBOOT relative to SW that turns off the high-side switch 2.1 V
CURRENT LIMITS
IL-HS High-side switch current limit(4) Duty cycle approaches 0% 8.9 10.3 11.5 A
IL-LS Low-side switch current limit 6.1 7.1 8.1 A
IL-ZC Zero-cross current limit. Positive current direction is out of the SW pin AUTO mode, static measurement 0.25 A
IL-NEG Negative current limit. Positive current direction is out of the SW pin FPWM operation –3 A
IPK_MIN_0 Minimum peak command in AUTO mode / device current rating Pulse duration < 100 ns 25%
IPK_MIN_100 Minimum peak command in AUTO mode / device current rating Pulse duration > 1 µs 12.5%
VHICCUP Ratio of FB voltage to in-regulation FB voltage Hiccup disabled during soft start 40%
POWER GOOD
PGDOV PGOOD upper threshold – rising % of VOUT setting 105% 107% 110%
PGDUV PGOOD lower threshold – falling % of VOUT setting 92% 94% 96.5%
PGDHYST PGOOD hysteresis % of VOUT setting 1.3%
VIN(PGD-VALID) Input voltage for proper PGOOD function 1.0 V
VPGD(LOW) Low-level PGOOD function output voltage 46-µA pullup to PGOOD, VIN = 1 V, VEN = 0 V 0.4 V
1-mA pullup to PGOOD, VEN = 0 V 0.4
2-mA pullup to PGOOD, VEN = 3.3 V 0.4
RPGD RDS(on) of PGOOD output 1-mA pullup to PGOOD, VEN = 0 V 17 40 Ω
1-mA pullup to PGOOD, VEN = 3.3 V 40 90 Ω
IOV Pulldown current at the SW node in an overvoltage condition 0.5 mA
THERMAL SHUTDOWN
TSHD Thermal shutdown rising threshold(1) 158 168 180 ℃
TSHD-HYS Thermal shutdown hysteresis(1) 10 ℃
(1) Parameter specified by design, statistical analysis and production testing of correlated parameters.  Not production tested. 
(2) IQ_VIN = IQ + IBIAS × (VOUT / VIN)
(3) This is the current used by the device while not switching, open loop, with FB pulled to +5% above nominal.  It does not represent the total input current to the converter while regulating.
(4) High-side current limit is a function of duty cycle.  High-side current limit value is highest at small duty cycle and less at higher duty cycle.