JAJSJT9A
October 2020 – December 2020
LM7310
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Switching Characteristics
14
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Input Reverse Polarity Protection
7.3.2
Undervoltage Protection (UVLO & UVP)
7.3.3
Overvoltage Lockout (OVLO)
7.3.4
Inrush Current control and Fast-trip
7.3.4.1
Slew Rate (dVdt) and Inrush Current Control
7.3.4.2
Fast-Trip During Steady State
7.3.5
Analog Load Current Monitor Output
7.3.6
Reverse Current Protection
7.3.7
Overtemperature Protection (OTP)
7.3.8
Fault Response
7.3.9
Power Good Indication (PG)
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Single Device, Self-Controlled
8.2.1
Typical Application
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
Setting Undervoltage and Overvoltage Thresholds
8.2.1.2.2
Setting Output Voltage Rise Time (tR)
8.2.1.2.3
Setting Power Good Assertion Threshold
8.2.1.2.4
Setting Analog Current Monitor Voltage (IMON) Range
8.2.1.3
Application Curves
8.3
Active ORing
8.4
Priority Power MUXing
8.5
USB PD Port Protection
8.6
Parallel Operation
9
Power Supply Recommendations
9.1
Transient Protection
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
ドキュメントの更新通知を受け取る方法
11.3
サポート・リソース
11.4
商標
11.5
静電気放電に関する注意事項
11.6
用語集
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RPW|10
MPQF568
サーマルパッド・メカニカル・データ
発注情報
jajsjt9a_oa
jajsjt9a_pm
7.2
Functional Block Diagram