JAJSJT9A October   2020  – December 2020 LM7310

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8.     14
    9. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Reverse Polarity Protection
      2. 7.3.2 Undervoltage Protection (UVLO & UVP)
      3. 7.3.3 Overvoltage Lockout (OVLO)
      4. 7.3.4 Inrush Current control and Fast-trip
        1. 7.3.4.1 Slew Rate (dVdt) and Inrush Current Control
        2. 7.3.4.2 Fast-Trip During Steady State
      5. 7.3.5 Analog Load Current Monitor Output
      6. 7.3.6 Reverse Current Protection
      7. 7.3.7 Overtemperature Protection (OTP)
      8. 7.3.8 Fault Response
      9. 7.3.9 Power Good Indication (PG)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Single Device, Self-Controlled
      1. 8.2.1 Typical Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Setting Undervoltage and Overvoltage Thresholds
          2. 8.2.1.2.2 Setting Output Voltage Rise Time (tR)
          3. 8.2.1.2.3 Setting Power Good Assertion Threshold
          4. 8.2.1.2.4 Setting Analog Current Monitor Voltage (IMON) Range
        3. 8.2.1.3 Application Curves
    3. 8.3 Active ORing
    4. 8.4 Priority Power MUXing
    5. 8.5 USB PD Port Protection
    6. 8.6 Parallel Operation
  9. 9 Power Supply Recommendations
    1. 9.1 Transient Protection
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.8 Fault Response

The following table summarizes the LM73100 response to various fault conditions.

Table 7-2 Fault Summary

Event

Protection Response

Fault Latched Internally

Overtemperature

Shutdown

Y

Undervoltage (UVP or UVLO)

Shutdown

N

Input Reverse Polarity

Shutdown

N

Overvoltage

Shutdown

N

Reverse Current

Reverse Current Blocking

N

Transient overcurrent during steady state

Shutdown

Y

Faults which are not latched internally are automatically cleared once the trigger condition goes away and thereafter the device recovers without any external intervention. Faults which are latched internally can be cleared either by power cycling the part (pulling VIN to 0 V and then above VUVP(R)) or by pulling the EN/UVLO pin voltage below VSD(F).

After a latched fault, pulling the EN/UVLO just below the UVLO threshold (VUVLO(F)) has no impact on the device.