JAJSE52B
November 2017 – May 2021
LM73605-Q1
,
LM73606-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Device Comparison
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Characteristics
7.7
Switching Characteristics
7.8
System Characteristics
7.9
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Synchronous Step-Down Regulator
8.3.2
Auto Mode and FPWM Mode
8.3.3
Fixed-Frequency Peak Current-Mode Control
8.3.4
Adjustable Output Voltage
8.3.5
Enable and UVLO
8.3.6
Internal LDO, VCC_UVLO, and BIAS Input
8.3.7
Soft Start and Voltage Tracking
8.3.8
Adjustable Switching Frequency
8.3.9
Frequency Synchronization and Mode Setting
8.3.10
Internal Compensation and CFF
8.3.11
Bootstrap Capacitor and VBOOT-UVLO
8.3.12
Power-Good and Overvoltage Protection
8.3.13
Overcurrent and Short-Circuit Protection
8.3.14
Thermal Shutdown
8.4
Device Functional Modes
8.4.1
Shutdown Mode
8.4.2
Standby Mode
8.4.3
Active Mode
8.4.3.1
CCM Mode
8.4.3.2
DCM Mode
8.4.3.3
PFM Mode
8.4.3.4
Fault Protection Mode
9
Layout
9.1
Layout Guidelines
9.1.1
Layout For EMI Reduction
9.1.2
Ground Plane
9.1.3
Optimize Thermal Performance
9.2
Layout Example
10
Device and Documentation Support
10.1
Device Support
10.1.1
Third-Party Products Disclaimer
10.1.2
Development Support
10.1.2.1
Custom Design With WEBENCH® Tools
10.2
Documentation Support
10.2.1
Related Documentation
10.3
Receiving Notification of Documentation Updates
10.4
Receiving Notification of Documentation Updates
10.5
Support Resources
10.6
サポート・リソース
10.7
Trademarks
10.8
Electrostatic Discharge Caution
10.9
Glossary
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RNP|30
MPQF448C
サーマルパッド・メカニカル・データ
RNP|30
QFND665
発注情報
jajse52b_oa
jajse52b_pm
8.2
Functional Block Diagram