JAJSMA4A July   2021  – February 2022 LM74501-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage
      2. 8.3.2 Charge Pump
      3. 8.3.3 Enable
      4. 8.3.4 Gate Driver
      5. 8.3.5 SW (Battery Voltage Monitoring)
      6. 8.3.6 Gate Discharge Timer
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Full Conduction Mode
      3. 8.4.3 VDS Clamp
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Reverse Battery Protection
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Design Considerations
        2. 9.2.2.2 MOSFET Selection
        3. 9.2.2.3 Gate Discharge Timer Capacitor Selection (CT)
        4. 9.2.2.4 Charge Pump VCAP, Input and Output Capacitance
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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発注情報

8.3.6 Gate Discharge Timer

The LM74501-Q1 has a unique gate discharge timer feature, which enables TVS less reverse polarity protection solution in case of ISO7637-2 pulse 1 event. An additional capacitor (CT) across external N-FET's GATE to SOURCE terminal keeps external N-FET on for specific time window even when input voltage falls below VPORF threshold of SOURCE pin or when the EN pin is pulled low. This gate discharge feature allows reverse current back to input source by keeping external MOSFET on for extended time duration set by gate discharge timer capacitor (CT) and enables automotive systems to meet TVS less ISO 7637-2 pulse 1 operation. Use Equation 2 to calculate the typical gate discharge time.

Equation 2. tD = –[RD × (CT + Ciss) × ln (VT / VGATE)]

Where

  • RD is the LM74501-Q1 internal GATE discharge resistor (typically 30 kΩ).
  • Ciss is the external MOSFET input capacitance.
  • CT is the timer capacitor connected between GATE and SOURCE of an external MOSFET.
  • VT is the gate-to-source threshold voltage of an external MOSFET.
  • VGATE is the nominal GATE pin voltage of LM74501-Q1 (12.4-V typical).
Figure 8-3 Typical Application Scenario During ISO7637-2 Pulse 1 Events

Figure 8-3 shows equivalent the LM74501-Q1 circuit operation during an ISO7637-2 pulse 1 event. Note that reverse current flows back to the input source from output loads such as a high-side switch followed by schottky diode or MOSFET H-bridge driving motor load. Thus, to achieve TVS less operation during ISO7637-2 pulse 1 events, output loads must be capable of withstanding the peak reverse current during ISO7637-2 pulse 1 event.

Figure 8-4 shows the TVS-less ISO7637-2 pulse 1 performance of the LM74501-Q1 with output loads capable of handling reverse current during an ISO7637-2 pulse 1 event, similar to loads configuration shown in Figure 8-4.

GUID-20210630-CA0I-40HK-HDRF-ZLFGWQBQDJSN-low.pngFigure 8-4 TVS Less Operation During ISO7637-2 Pulse 1

The other short duration transient events such as ISO7637-2 pulse 2A, 3A, or 3B usually get filtered out by input and output capacitors and do not affect the system performance.

For the loads that cannot handle peak reverse current during an ISO 7637-2 pulse 1 transient event but can handle negative voltage for a short duration, a schottky diode capable of handling peak reverse current can be placed from output to ground to clamp the output voltage to negative forward voltage drop of the Schottky diode (–VF).