JAJSMX2B
September 2021 – July 2022
LM74721-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Reverse Battery Protection (A, C, GATE)
8.3.1.1
Input TVS Less Operation: VDS Clamp
8.3.2
Load Disconnect Switch Control (PD)
8.3.3
Overvoltage Protection and Battery Voltage Sensing (VSNS, SW, OV)
8.3.4
Boost Regulator
8.4
Shutdown Mode
9
Application and Implementation
9.1
Application Information
9.2
Typical 12-V Reverse Battery Protection Application
9.2.1
Design Requirements for 12-V Battery Protection
9.2.2
Detailed Design Procedure
9.2.2.1
Boost Converter Components (C2, C3, L1)
9.2.2.2
Input and Output Capacitance
9.2.2.3
Hold-Up Capacitance
9.2.2.4
MOSFET Selection: Q1
9.2.3
Application Curves
9.3
What to Do and What Not to Do
10
Power Supply Recommendations
10.1
Transient Protection
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Receiving Notification of Documentation Updates
12.2
サポート・リソース
12.3
Trademarks
12.4
Electrostatic Discharge Caution
12.5
Glossary
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
DRR|12
サーマルパッド・メカニカル・データ
発注情報
jajsmx2b_oa
9.2.3
Application Curves
Figure 9-4
ISO 7637-2 Pulse 1
Time (100 µs/DIV)
Figure 9-6
Response to ISO 7637-2 Pulse 2A
Time (100 ms/DIV)
Figure 9-8
Response to LV124 E-06 (AC Superimpose Test)
Time (4 ms/DIV)
Figure 9-5
Response to ISO 7637-2 Pulse 1
Time (200 ms/DIV)
Figure 9-7
Response to ISO 7637-2 Pulse 2B
Time (40 µs/DIV)
Figure 9-9
Response to LV124 E-10 (Input Micro Short, 100 us)