JAJSM84B december   2022  – july 2023 LM74900-Q1 , LM74910-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 スイッチング特性
    7. 7.7 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Charge Pump
      2. 9.3.2 Dual Gate Control (DGATE, HGATE)
        1. 9.3.2.1 Reverse Battery Protection (A, C, DGATE)
        2. 9.3.2.2 Load Disconnect Switch Control (HGATE, OUT)
      3. 9.3.3 Overcurrent Protection (CS+, CS-, ILIM, IMON, TMR)
        1. 9.3.3.1 Pulse Overload Protection, Circuit Breaker
        2. 9.3.3.2 Overcurrent Protection With Latch-Off
        3. 9.3.3.3 Short Circuit Protection (ISCP)
        4. 9.3.3.4 Analog Current Monitor Output (IMON)
      4. 9.3.4 Undervoltage Protection, Overvoltage Protection, and Battery Voltage Sensing (UVLO, OV, SW)
      5. 9.3.5 Low IQ SLEEP Mode (SLEEP)
      6. 9.3.6 Ultra Low IQ Shutdown (EN)
  11. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical 12-V Reverse Battery Protection Application
      1. 10.2.1 Design Requirements for 12-V Battery Protection
      2. 10.2.2 Automotive Reverse Battery Protection
        1. 10.2.2.1 Input Transient Protection: ISO 7637-2 Pulse 1
        2. 10.2.2.2 AC Super Imposed Input Rectification: ISO 16750-2 and LV124 E-06
        3. 10.2.2.3 Input Micro-Short Protection: LV124 E-10
      3. 10.2.3 Detailed Design Procedure
        1. 10.2.3.1 Design Considerations
        2. 10.2.3.2 Charge Pump Capacitance VCAP
        3. 10.2.3.3 Input and Output Capacitance
        4. 10.2.3.4 Hold-Up Capacitance
        5. 10.2.3.5 Selection of Current Sense Resistor, RSNS
        6. 10.2.3.6 Selection of Scaling Resistor (RSET) and Short-Circuit Protection Setting Resistor (RSCP)
        7. 10.2.3.7 Overcurrent Limit (ILIM), Circuit Breaker Timer (TMR), and Current Monitoring Output (IMON) Selection
        8. 10.2.3.8 Overvoltage Protection and Battery Monitor
      4. 10.2.4 MOSFET Selection: Blocking MOSFET Q1
      5. 10.2.5 MOSFET Selection: Hot-Swap MOSFET Q2
      6. 10.2.6 TVS Selection
      7. 10.2.7 Application Curves
    3. 10.3 Addressing Automotive Input Reverse Battery Protection Topologies With LM749x0-Q1
    4. 10.4 Power Supply Recommendations
      1. 10.4.1 Transient Protection
      2. 10.4.2 TVS Selection for 12-V Battery Systems
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
  12. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-20210705-CA0I-L3JJ-NJMF-Z5DLGMKRZFWW-low.svgFigure 6-1 RGE Package,24-Pin VQFN(Transparent Top View)
Table 6-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
DGATE1ODiode controller gate drive output. Connect to the GATE of the external MOSFET.
A2IAnode of the ideal diode. Connect to the source of the external MOSFET.
SW3IVoltage sensing disconnect switch terminal. VSNS and SW are internally connected through a switch. Use SW as the top connection of the battery sensing or OV resistor ladder network. When EN is pulled low, the switch is OFF disconnecting the resistor ladder from the battery line thereby cutting off the leakage current. If the internal disconnect switch between VSNS and SW is not used then short them together and connect to VS pin.
UVLO4IAdjustable undervoltage threshold input. Connect a resistor ladder across SW to UVLO terminal to GND. When the voltage at UVLO goes below the undervoltage cut-off threshold then the HGATE is pulled low turning OFF the HSFET. HGATE turns ON when the sense voltage goes above the UVLO falling threshold.
OV5IAdjustable overvoltage threshold input. Connect a resistor ladder across SW to OV terminal. When the voltage at OVP exceeds the overvoltage cut-off threshold then the HGATE is pulled low turning OFF the HSFET. HGATE turns ON when the sense voltage goes below the OVP falling threshold.
EN6IEN input. Connect to VS pin for always ON operation. Can be driven externally from a microcontroller I/O. Pulling it low below V(ENF) makes the device enter into low Iq shutdown mode.
SLEEP7IActive low SLEEP mode input. Can be driven from the microcontroller. When pulled low device enters into low power state with charge pump and gate drive turned off. Internal bypass switch provides output voltage with limited current capacity.
NC8—No connect.
TMR9IFault timer input. A capacitor across TMR pin to GND sets the times for fault warning, fault turn off (FLT), and retry periods. Leave it open for fastest setting. Connect TMR to GND to disable overcurrent protection.
IMON10OAnalog current monitor output. This pin sources a scaled down ratio of current through the external current sense resistor RSNS. A resistor from this pin to GND converts current to proportional voltage. If unused, leave it floating.
ILIM11IOvercurrent detection setting. A resistor across ILIM to GND sets the overcurrent comparator threshold. Connect ILIM to GND if overcurrent protection feature is not desired.
FLT12OOpen drain fault output. FLT pin is pulled low in case of UVLO, OV, OCP, or SCP event.
GND13GConnect to the system ground plane.
HGATE14OGATE driver output for the HSFET. Connect to the GATE of the external FET.
OUT15IConnect to the output rail (external MOSFET source).
SLEEP_OV16ISLEEP mode overvoltage protection pin. Connect this pin to VS for overvoltage cut-off functionality. Connect to OUT for overvoltage clamp functionality.
NC17—No connect.
ISCP18I

Short circuit detection threshold setting.

Leave ISCP floating if short circuit protection is not desired. When ISCP is connected to CS+, device sets an internal fix threshold of 20 mV.

CS–19ICurrent sense negative input.
CS+20ICurrent sense positive input. Connect a TBD resistor across CS+ to the external current sense resistor.
NC21—No connect.
VS22PInput power supply to the IC. Connect VS to middle point of the common drain back to back MOSFET configuration. Connect a 100-nF capacitor across VS and GND pins.
CAP23OCharge pump output. Connect a 100-nF capacitor across CAP and VS pins.
C24ICathode of the ideal diode. Connect to the drain of the external MOSFET.
RTNThermal Pad—Leave exposed pad floating. Do not connect to GND plane.
(1) I = input, O = output, I/O = input and output, P = power, G = ground