JAJSE81B December   2017  – October 2019 LM76002-Q1 , LM76003-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
    2.     効率と出力電流との関係 (VOUT＝5V、fSW＝400kHz、自動モード)
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 System Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency, Peak-Current-Mode Control
      2. 7.3.2  Light Load Operation Modes — PFM and FPWM
      3. 7.3.3  Adjustable Output Voltage
      4. 7.3.4  Enable (EN Pin) and UVLO
      5. 7.3.5  Internal LDO, VCC UVLO, and Bias Input
      6. 7.3.6  Soft Start and Voltage Tracking (SS/TRK)
      7. 7.3.7  Adjustable Switching Frequency (RT) and Frequency Synchronization
      8. 7.3.8  Minimum On-Time, Minimum Off-Time, and Frequency Foldback at Dropout Conditions
      9. 7.3.9  Internal Compensation and CFF
      10. 7.3.10 Bootstrap Voltage and VBOOT UVLO (BOOT Pin)
      11. 7.3.11 Power Good and Overvoltage Protection (PGOOD)
      12. 7.3.12 Overcurrent and Short-Circuit Protection
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
      4. 7.4.4 CCM Mode
      5. 7.4.5 DCM Mode
      6. 7.4.6 Light Load Mode
      7. 7.4.7 Foldback Mode
      8. 7.4.8 Forced Pulse-Width-Modulation Mode
      9. 7.4.9 Self-Bias Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Output Voltage Setpoint
        3. 8.2.2.3  Switching Frequency
        4. 8.2.2.4  Input Capacitors
        5. 8.2.2.5  Inductor Selection
        6. 8.2.2.6  Output Capacitor Selection
        7. 8.2.2.7  Feed-Forward Capacitor
        8. 8.2.2.8  Bootstrap Capacitors
        9. 8.2.2.9  VCC Capacitors
        10. 8.2.2.10 BIAS Capacitors
        11. 8.2.2.11 Soft-Start Capacitors
        12. 8.2.2.12 Undervoltage Lockout Setpoint
        13. 8.2.2.13 PGOOD
        14. 8.2.2.14 Synchronization
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Highlights
      2. 10.1.2 Compact Layout for EMI Reduction
      3. 10.1.3 Ground Plane and Thermal Considerations
      4. 10.1.4 Feedback Resistors
    2. 10.2 Layout Example
    3. 10.3 Thermal Design
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.4 Enable (EN Pin) and UVLO

System UVLO by EN and VCC_UVLO voltage on the EN pin (VEN) controls the ON/OFF functionality of the LM76002-Q1/LM76003-Q1. Applying a voltage less than 0.3 V to the EN input shuts down the operation of the LM76002-Q1/LM76003-Q1. In shutdown mode the quiescent current drops to typically 1.2 µA at VIN = 24 V.

The internal LDO output voltage VCC is turned on when VEN_VOUT_H is higher than 1.15 V. The LM76002-Q1/LM76003-Q1 switching action and output regulation are enabled when VEN is greater than 1.204 V (typical). The LM76002-Q1/LM76003-Q1 supplies regulated output voltage when enabled and output current up to 2.5 A/3.5 A. The EN pin is an input and cannot be open circuit or floating. The simplest way to enable the operation of the LM76002-Q1/LM76003-Q1 is to connect the EN pin to PVIN pins directly. This allows self-start-up of the LM76002-Q1/LM76003-Q1 when VIN is within the operation range.

Many applications may benefit from the employment of an enable divider RENT and RENB (see Figure 12) to establish a precision system UVLO level for the stage. System UVLO can be used for supplies operating from utility power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such as a battery. An external logic signal can also be used to drive EN input for system sequencing and protection.

LM76002-Q1 LM76003-Q1 system_UVLO_enable_div.gifFigure 12. VIN UVLO

With a selected RENT, the RENB can be calculated by:

Equation 4. LM76002-Q1 LM76003-Q1 eq_Renb_calculation.gif

where

  • VIN_ON_H is the desired supply voltage threshold to turn on this device
  • VEN_VOUT_H could be taken from device data sheet

Note that the divider adds to supply quiescent current by VIN / (RENT + RENB). Small RENT and RENB values add more quiescent current loss. However, large divider values make the node more sensitive to noise. RENT in the hundreds of kΩ range is a good starting point.