JAJSGF7G May   2010  – November 2018 LM98640QML-SP

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings    
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information         
    5. 6.5 Quality Conformance Inspection
    6. 6.6 LM98640QML-SP Electrical Characteristics
    7. 6.7 AC Timing Specifications
    8. 6.8 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sampling Modes
        1. 7.3.1.1 Sample & Hold Mode
          1. 7.3.1.1.1 Sample & Hold Mode CLAMP/SAMPLE Adjust
        2. 7.3.1.2 CDS Mode
          1. 7.3.1.2.1 CDS Mode Bimodal Offset
          2. 7.3.1.2.2 CDS Mode CLAMP/SAMPLE Adjust
      2. 7.3.2 Input Bias and Clamping
        1. 7.3.2.1 Sample and Hold Mode Biasing
        2. 7.3.2.2 CDS Mode Biasing
        3. 7.3.2.3 VCLP DAC
      3. 7.3.3 Programmable Gain
        1. 7.3.3.1 CDS/SH Stage Gain
        2. 7.3.3.2 PGA Gain Plots
      4. 7.3.4 Programmable Analog Offset Correction
      5. 7.3.5 Analog to Digital Converter
      6. 7.3.6 LVDS Output
        1. 7.3.6.1 LVDS Output Voltage
        2. 7.3.6.2 LVDS Output Modes
        3. 7.3.6.3 TXFRM Output
          1. 7.3.6.3.1 Output Mode 1 - Dual Lane
          2. 7.3.6.3.2 Output Mode 2 - Quad Lane
      7. 7.3.7 Clock Receiver
      8. 7.3.8 Power Trimming
    4. 7.4 Device Functional Mode
      1. 7.4.1 Powerdown Modes
      2. 7.4.2 LVDS Test Modes
        1. 7.4.2.1 Test Mode 0 - Fixed Pattern
        2. 7.4.2.2 Test Mode 1 - Horizontal Gradient
        3. 7.4.2.3 Test Mode 2 - Vertical Gradient
        4. 7.4.2.4 Test Mode 3 - Lattice Pattern
        5. 7.4.2.5 Test Mode 4 - Stripe Pattern
        6. 7.4.2.6 Test Mode 5 - LVDS Test Pattern (Synchronous)
        7. 7.4.2.7 Test Mode 6 - LVDS Test Pattern (Asynchronous)
        8. 7.4.2.8 Pseudo Random Number Mode
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Writing to the Serial Registers
      3. 7.5.3 Reading the Serial Registers
      4. 7.5.4 Serial Interface Timing Details
    6. 7.6 Register Maps
      1. 7.6.1 Register Definitions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Total Ionizing Dose
      2. 8.1.2 Single Event Latch-Up and Functional Interrupt
      3. 8.1.3 Single Event Effects
    2. 8.2 Typical Application
      1. 8.2.1 Sample/Hold Mode
    3. 8.3 Initialization Set Up
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Power Planes
      2. 9.1.2 Bypass Capacitors
      3. 9.1.3 Ground Plane
      4. 9.1.4 Thermal Management
  10. 10デバイスおよびドキュメントのサポート
    1. 10.1 デバイス・サポート
      1. 10.1.1 開発サポート
        1. 10.1.1.1 評価ボード
        2. 10.1.1.2 レジスタのプログラミング用ソフトウェア
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 コミュニティ・リソース
    4. 10.4 輸出管理に関する注意事項
    5. 10.5 商標
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 Glossary
  11. 11メカニカル、パッケージ、および注文情報
    1. 11.1 エンジニアリング・サンプル

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • NBB|68
サーマルパッド・メカニカル・データ
発注情報

6.6 LM98640QML-SP Electrical Characteristics(3)(1)

The following specifications apply for VDD33 = 3.3 V, VDD18 = 1.8 V, CL = 10 pF, and fINCLK = 40 MHz unless otherwise specified.
PARAMETER TEST CONDITIONS NOTES SUB-
GROUPS		 MIN TYP(2) MAX UNIT
CMOS DIGITAL INPUT DC SPECIFICATIONS (SCLK, SEN, SDI, CLPIN)
VIH Logical “1” Input Voltage 1, 2, 3 2.0 V
VIL Logical “0” Input Voltage 1, 2, 3 0.8 V
IIH Logical “1” Input Current
VIH = VDD33		 CLPIN 1, 2, 3 70 100 μA
SCLK, SDI 40 300 nA
SEN 0.2 6 μA
IIL Logical “0” Input Current
VIL = VSS		 CLPIN 1, 2, 3 –300 –85 nA
SCLK, SDI –300 –50 nA
SEN –100 –70 μA
CMOS DIGITAL OUTPUT DC SPECIFICATIONS (SDO)
VOH Logical "1" Output Voltage IOUT = –0.5 mA 1, 2, 3 1.8 1.93 V
VOL Logical "0" Output Voltage IOUT = 1.6 mA 1, 2, 3 0.05 0.2 V
IOH Output Leakage Current VOUT = VDD 1, 2, 3 20 50 nA
IOL Output Leakage Current VOUT = VSS 1, 2, 3 –50 –20 nA
LVDS CLOCK RECEIVER DC SPECIFICATIONS (INCLK+ and INCLK– Pins)
VIHL Differential LVDS Clock RL = 100 Ω 1, 2, 3 100 250 mV
High Threshold Voltage VCM (LVDS Input Common Mode Voltage) = 1.25 V
VILL Differential LVDS Clock RL = 100 Ω 1, 2, 3 –250 –100 mV
Low Threshold Voltage VCM (LVDS Input Common Mode Voltage) = 1.25 V
IIHL Differential LVDS Clock Input Current VIH = VDD33 1, 2, 3 70 100 μA
IILL Differential LVDS Clock Input Current VIL = VSS 1, 2, 3 –49 –34 μA
LVDS OUTPUT DC SPECIFICATIONS
VOD Differential Output Voltage LVDS Output Modes =
0000 x100
RL = 100 Ω		 1, 2, 3 210 275 410 mV
VOS LVDS Output Offset Voltage 1, 2, 3 1.05 1.19 1.3 V
VOD Differential Output Voltage LVDS Output Modes =
0000 x101
RL = 100 Ω		 1, 2, 3 250 325 460 mV
VOS LVDS Output Offset Voltage 1, 2, 3 1.05 1.19 1.3 V
VOD Differential Output Voltage LVDS Output Modes =
0000 x110
RL = 100 Ω		 1, 2, 3 300 377 535 mV
VOS LVDS Output Offset Voltage 1, 2, 3 0.95 1.1 1.2 V
VOD Differential Output Voltage LVDS Output Modes =
0000 x111
RL = 100 Ω		 1, 2, 3 350 425 590 mV
VOS LVDS Output Offset Voltage 1, 2, 3 0.95 1.1 1.2 V
IOH LVDS Output Leakage Current 1, 2, 3 4.25 5 μA
IOL LVDS Output Leakage Current 1, 2, 3 –5 –4.29 μA
IOS Output Short Circuit Current VOUT = 0 V, RL = 100 Ω 1, 2, 3 40 50 mA
POWER SUPPLY SPECIFICATIONS (see Power Trimming section for PGA and ADC Power Trimming register settings)
IA VDD33 Analog Supply Current
Dual Channel
Power optimized for
PGA Gain = 1-4x 		Powerdown Control Reg
= 0x00
5 MHz 1, 2, 3 51.5 58 mA
15 MHz 61.3
25 MHz 69.6
40 MHz 1, 2, 3 87.6 98
VDD33 Analog Supply Current
Dual Channel
Power optimized for
PGA Gain = 1-8x 		Powerdown Control Reg
= 0x00
5 MHz 1, 2, 3 51.5 58 mA
15 MHz 61.3
25 MHz 72.9
40 MHz 1, 2, 3 91.3 103
VDD33 Analog Supply Current
Single Channel
Power optimized for
PGA Gain = 1-4x 		Powerdown Control Reg
= 0x15 (CH1 PD) or
= 0x2A (CH2 PD)
5 MHz 1, 2, 3 29.5 35 mA
15 MHz 36.1
25 MHz 42
40 MHz 1, 2, 3 53.7 60
VDD33 Analog Supply Current
Single Channel
Power optimized for
PGA Gain = 1-8x 		Powerdown Control Reg
= 0x15 (CH1 PD) or
= 0x2A (CH2 PD)
5 MHz 1, 2, 3 29.5 35 mA
15 MHz 36.1
25 MHz 43.8
40 MHz 1, 2, 3 55.6 64
VDD33 Analog Supply Current
Powerdown 		Powerdown Control Reg
= 0x80		 1, 2, 3 2.85 3.85 mA
ID VDD18 Digital Supply Current
LVDS Quad Lane Mode
LVDS Output Mode Reg
= 0x0E		 5 MHz 36 mA
15 MHz 39
25 MHz 42
40 MHz 45
VDD18 Digital Supply Current 5 MHz 1, 2, 3 23.5 29 mA
15 MHz 25.5
25 MHz 27.5
40 MHz 1, 2, 3 30.5 37
VDD18 Digital Supply Current
Powerdown 		Powerdown Control
Reg = 0x80		 1, 2, 3 1.2 3.0 mA
PWR Average Power Dissipation
Power optimized for
PGA Gain = 1-4x
Dual Channel
LVDS Dual Lane Mode		 5 MHz 1, 2, 3 212 244 mW
15 MHz 250
25 MHz 280
40 MHz 1, 2, 3 345 390
Average Power Dissipation
Power optimized for
PGA Gain = 1-8x
Dual Channel
LVDS Dual Lane Mode		 5 MHz 1, 2, 3 212 244 mW
15 MHz 250
25 MHz 290
40 MHz 1, 2, 3 356 407
PSRR Dynamic Power Supply Rejection Ratio
CDS Gain = 1x
PGA Gain = 1x		 200 mVpp, 200 KHz See(5) –72.3 dB
200 mVpp, 500 KHz –72
200 mVpp, 1 MHz –71
200 mVpp, 1.5 MHz –68
200 mVpp, 2 MHz –66
INTERNAL REFERENCE SPECIFICATIONS
VREFBG Reference Voltage See(4) 1.218 V
Reference Tolerance
(chip to chip)		 See(4) ±2%
RREFBG Reference Impedance See(4) 20 kΩ
VREFTC Temperature Coefficient 25°C to 125°C 80 ppm/°C
–55°C to 25°C 50
INPUT SAMPLING CIRCUIT SPECIFICATIONS
VIN Input Voltage Level CDS Gain = 1x, PGA Gain = 1x 1, 2, 3 2 Vp-p
CDS Gain = 2x, PGA Gain= 1 x 1
CDS Gain = 1x, PGA Gain = 0.7x 2.85
VRESET Reset Feed Through 500 mV
IIN_SH Sample and Hold Mode
Input Leakage Current		 CDS Gain = 1x See(4) 384 μA
OSX = VDD33 (OSX = VSS)
CDS Gain = 2x See(4) –475 µA
OSX = VDD33 (OSX = VSS)
CSH Sample/Hold Mode CDS Gain = 1x See(4) 4 pF
Equivalent Input Capacitance
(see Figure 20) CDS Gain = 2x See(4) 8 pF
IIN_CDS CDS Mode OSX = VDD33 (OSX = VSS) See(4) 300 nA
Input Leakage Current
RCLPIN CLPIN Switch Resistance See(4) 16 Ω
(OSX to VCLP Node in Figure 17)
VCLP REFERENCE CIRCUIT SPECIFICATION
VCLP DAC Resolution 1, 2, 3 5 5 Bits
VCLP DAC Step Size 1, 2, 3 96 98 102 mV
VVCLP VCLP DAC Voltage Min Output VCLP Control Register = 1, 2, 3 194 224 298 mV
0110 0000
VCLP DAC Voltage Max Output VCLP Control Register = 1, 2, 3 2.99 3.07 3.11 V
0111 1101
ISC VCLP DAC Short Circuit Output Current VCLP Control Register = 33 mA
011x xxxx
COARSE ANALOG OFFSET DAC SPECIFICATIONS
Resolution ±8 Bits
Offset Adjustment Range Referred to AFE Input
CDS Gain = 1x		 Minimum DAC Code = 0x000 1, 2, 3 –264 –262 –251 mV
Maximum DAC Code = 0x1FF 251 263 266
Offset Adjustment Range Referred to AFE Input
CDS Gain = 2x		 Minimum DAC Code = 0x000 1, 2, 3 –132 –131 –126 mV
Maximum DAC Code = 0x1FF 126 131 133
Offset Adjustment Range
Referred to AFE Output		 Minimum DAC Code = 0x000 1, 2, 3 –2162 –2146 –2058 LSB
Maximum DAC Code = 0x1FF 2058 2154 2176
DAC Step Size
CDS Gain = 1x		 Input Referred 1 mV
DAC Step Size
CDS Gain = 1x		 Output Referred 8 LSB
DNL Differential Non-Linearity CDS Gain = 1x or 2x 40 MHz 1, 2, 3 –1.1 ±0.97 1.1 LSB
INL Integral Non-Linearity CDS Gain = 1x or 2x 40 MHz 1, 2, 3 –2.8 ±1.5 2.80 LSB
FINE ANALOG OFFSET DAC SPECIFICATIONS
Resolution ±8 Bits
Offset Adjustment Range Referred to AFE Input
CDS Gain = 1x		 Minimum DAC Code = 0x000 1, 2, 3 –5.9 –4.6 –3.1 mV
Maximum DAC Code = 0x1FF 4.3 5.3 6.8
Offset Adjustment Range Referred to AFE Input
CDS Gain = 2x		 Minimum DAC Code = 0x000 1, 2, 3 –2.9 –2.3 –1.5 mV
Maximum DAC Code = 0x1FF 2.1 2.6 3.4
Offset Adjustment Range
Referred to AFE Output		 Minimum DAC Code = 0x000 1, 2, 3 –48 –38 –25 LSB
Maximum DAC Code = 0x1FF 35 43 56
DAC Step Size
CDS Gain = 1x		 Input Referred 20 uV
DAC Step Size
CDS Gain = 1x		 Output Referred 0.16 LSB
DNL Differential Non-Linearity ±1 LSB
INL Integral Non-Linearity ±2.2 LSB
PGA SPECIFICATIONS
Gain Resolution 1, 2, 3 8 Bits
Monotonicity See(4)
Maximum Gain CDS Gain = 1x 1, 2, 3 7.92 8.3 8.78 V/V
CDS Gain = 1x 1, 2, 3 17.99 18.4 18.88 dB
Minimum Gain CDS Gain = 1x 1, 2, 3 0.62 0.64 0.66 V/V
CDS Gain = 1x 1, 2, 3 –4.15 –3.8 –3.54 dB
PGA Function Gain (V/V) = (180/(277-PGA Code))
Gain (dB) = 20LOG10(180/(277-PGA Code))
Channel Matching Minimum PGA Gain 1, 2 95.2% 99.0%
3 94.0% 99.0%
Maximum PGA Gain 1, 2 95.2% 99.0%
3 94.0% 99.0%
ADC SPECIFICATIONS
VREFT Top of Reference 2.0 V
VREFB Bottom of Reference 1.0 V
VREFT - VREFB Differential Reference Voltage 1.0 V
Overrange Output Code 1, 2, 3 16383 16383 Code
Underrange Output Code 1, 2, 3 0 0 Code
FULL CHANNEL PERFORMANCE SPECIFICATIONS
DNL Differential Non-Linearity 5 MHz 1, 2, 3 –1.03 0.78 1.53 LSB
5 MHz CDS 1, 2, 3 –1.20 1.0 2.24
15 MHz 0.78
25 MHz 0.78
40 MHz 1, 2, 3 –1.03 0.78 1.45
INL Integral Non-Linearity 5 MHz 1, 2, 3 –5.38 1.7 4.38 LSB
5 MHz CDS 1, 2, 3 –3.41 1.7 5.15
15 MHz 1.9
25 MHz 2.4
40 MHz 1, 2, 3 –9.9 6.0 7.34
Noise Noise Floor CDS Gain = 1x
PGA Gain = FE		 5 MHz 1, 2 –66.0 –64.6 dB
3 –65.0 –62.5
15 MHz –66.0 dB
–66.0
25 MHz –66.0 dB
–65.0
40 MHz 1, 2 –66.0 –64.6 dB
3 –66.5 –65.7
Noise Floor CDS Gain = 1x
PGA Gain = FE		 5 MHz 1, 2 8.20 9.6 LSB
3 9.15 11.9
15 MHz 8.20 LSB
8.20
25 MHz 8.20 LSB
9.15
40 MHz 1, 2 8.20 9.45 LSB
3 7.70 8.5
Noise Floor CDS Gain = 1x
PGA Gain = 61		 5 MHz 1, 2, 3 –79 –78 dB
15 MHz –79 dB
25 MHz –79 dB
40MHz 1, 2, 3 –79 –78 dB
Noise Floor CDS Gain = 1x
PGA Gain = 61		 5 MHz 1, 2, 3 1.8 2.05 LSB
15 MHz 1.8 LSB
25 MHz 1.8 LSB
40 MHz 1, 2, 3 1.8 2.05 LSB
Channel to Channel Crosstalk 5 MHz 4, 5, 6 –79 –77 dB
15 MHz –86
25 MHz –79
40 MHz 4, 5, 6 –76 –74
BMD CDS Mode Bimodal Offset
CDS Gain = 1x
PGA Gain = 8x		 5 MHz 1, 2, 3 2.2 6.0 mV
15 MHz 2.1
25 MHz 2.2
40 MHz 1, 2, 3 2.3 6.0
CDS Mode Bimodal Offset
CDS Gain = 1x
PGA Gain = 1x		 5 MHz 1, 2, 3 0.35 1 mV
15 MHz 0.29
25 MHz 0.33
40 MHz 1, 2, 3 0.4 1.05
SNR Signal-to-Noise Ratio 5 MHz 4, 5 66.0 67.4 dB
6 63.0 64.2
15 MHz 68.0 dB
64.2
25 MHz 68.5 dB
64.2
40 MHz 4, 5 66.5 68.5 dB
6 62.0 64.0
THD Total Harmonic Distortion 5 MHz 4, 5 –71.4 –69.0 dB
6 –69.9 –67.8
15 MHz –75.1 dB
–73.9
25 MHz –68.9 dB
–68.2
40 MHz 4, 5 –62.0 –60.0 dB
6 –62.0 –60.0
SFDR Spurious-Free Dynamic Range 5 MHz 4, 5 69.4 71.5 dB
6 68.4 70.4
15 MHz 76.0 dB
76.0
25 MHz 69.0 dB
69.0
40 MHz 4, 5 60.0 62.0 dB
6 60.0 62.0
SINAD Signal-to-Noise Plus Distortion Ratio 5 MHz 4, 5 65.0 67.0 dB
6 62.0 64.5
15 MHz 68.0 dB
64.5
25 MHz 66.0 dB
64.5
40 MHz 4, 5 59.0 61.0 dB
6 59.0 60.5
ENOB Effective Number of Bits 5 MHz 4, 5 10.5 10.8 Bits
6 10.0 10.4
15 MHz 11.0 Bits
10.4
25 MHz 10.7 Bits
10.5
40 MHz 4, 5 9.5 9.8 Bits
6 9.5 9.8
(1) When the input voltage (VIN) at any pin exceeds the power supplies (VIN < VSS or VIN > VDD33), the current at that pin should be limited to 25 mA. The 50-mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25 mA to two.
(2) Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured.
(3) The analog inputs are protected as shown below. Input voltage magnitudes beyond the supply rails will not damage the device, provided the current is limited per Note 2 under the LM98640QML-SP Electrical Characteristics. However, input errors will be generated If the input goes above VDD33 and below VSS.LM98640QML-SP 30064771.gif
(4) This parameter is ensured by design and/or characterization and is not tested.
(5) Dynamic Power Supply Rejection Ratio is performed by injecting a 200-mVpp sine wave ac coupled to the analog supply pin. The LM98640QML-SP inputs are left floating in CDS mode and an FFT is captured. The spur ensured by the injected signal is recorded.