JAJSGF7G May   2010  – November 2018 LM98640QML-SP

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings    
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information         
    5. 6.5 Quality Conformance Inspection
    6. 6.6 LM98640QML-SP Electrical Characteristics
    7. 6.7 AC Timing Specifications
    8. 6.8 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sampling Modes
        1. 7.3.1.1 Sample & Hold Mode
          1. 7.3.1.1.1 Sample & Hold Mode CLAMP/SAMPLE Adjust
        2. 7.3.1.2 CDS Mode
          1. 7.3.1.2.1 CDS Mode Bimodal Offset
          2. 7.3.1.2.2 CDS Mode CLAMP/SAMPLE Adjust
      2. 7.3.2 Input Bias and Clamping
        1. 7.3.2.1 Sample and Hold Mode Biasing
        2. 7.3.2.2 CDS Mode Biasing
        3. 7.3.2.3 VCLP DAC
      3. 7.3.3 Programmable Gain
        1. 7.3.3.1 CDS/SH Stage Gain
        2. 7.3.3.2 PGA Gain Plots
      4. 7.3.4 Programmable Analog Offset Correction
      5. 7.3.5 Analog to Digital Converter
      6. 7.3.6 LVDS Output
        1. 7.3.6.1 LVDS Output Voltage
        2. 7.3.6.2 LVDS Output Modes
        3. 7.3.6.3 TXFRM Output
          1. 7.3.6.3.1 Output Mode 1 - Dual Lane
          2. 7.3.6.3.2 Output Mode 2 - Quad Lane
      7. 7.3.7 Clock Receiver
      8. 7.3.8 Power Trimming
    4. 7.4 Device Functional Mode
      1. 7.4.1 Powerdown Modes
      2. 7.4.2 LVDS Test Modes
        1. 7.4.2.1 Test Mode 0 - Fixed Pattern
        2. 7.4.2.2 Test Mode 1 - Horizontal Gradient
        3. 7.4.2.3 Test Mode 2 - Vertical Gradient
        4. 7.4.2.4 Test Mode 3 - Lattice Pattern
        5. 7.4.2.5 Test Mode 4 - Stripe Pattern
        6. 7.4.2.6 Test Mode 5 - LVDS Test Pattern (Synchronous)
        7. 7.4.2.7 Test Mode 6 - LVDS Test Pattern (Asynchronous)
        8. 7.4.2.8 Pseudo Random Number Mode
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Writing to the Serial Registers
      3. 7.5.3 Reading the Serial Registers
      4. 7.5.4 Serial Interface Timing Details
    6. 7.6 Register Maps
      1. 7.6.1 Register Definitions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Total Ionizing Dose
      2. 8.1.2 Single Event Latch-Up and Functional Interrupt
      3. 8.1.3 Single Event Effects
    2. 8.2 Typical Application
      1. 8.2.1 Sample/Hold Mode
    3. 8.3 Initialization Set Up
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Power Planes
      2. 9.1.2 Bypass Capacitors
      3. 9.1.3 Ground Plane
      4. 9.1.4 Thermal Management
  10. 10デバイスおよびドキュメントのサポート
    1. 10.1 デバイス・サポート
      1. 10.1.1 開発サポート
        1. 10.1.1.1 評価ボード
        2. 10.1.1.2 レジスタのプログラミング用ソフトウェア
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 コミュニティ・リソース
    4. 10.4 輸出管理に関する注意事項
    5. 10.5 商標
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 Glossary
  11. 11メカニカル、パッケージ、および注文情報
    1. 11.1 エンジニアリング・サンプル

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • NBB|68
サーマルパッド・メカニカル・データ
発注情報

6.7 AC Timing Specifications

The following specifications apply for VDD33 = 3.3 V, VDD18 = 1.8 V, CL = 10 pF, and fINCLK = 15 MHz unless otherwise specified.
PARAMETER TEST CONDITIONS NOTES SUB-
GROUPS		 MIN TYP(2) MAX UNIT
INPUT CLOCK TIMING SPECIFICATIONS
fINCLK Input clock frequency INCLK = ADCCLK 9, 10, 11 5 40 MHz
(ADC Rate Clock)
Tdc Input clock duty cycle 9, 10, 11 40/60% 50/50% 60/40%
tLAT Pipeline latency See(1) 10 TADC
LVDS OUTPUT TIMING SPECIFICATIONS
tDOD Data output delay fINCLK = 40 MHz
INCLK = ADCCLK
(ADC Rate Clock)
LVDS Output Specifications not tested in production. Min/Max ensured by design, characterization and statistical analysis.		 9, 10, 11 6.44 7.50 ns
tDSO Dual lane mode 9, 10, 11 0.45 0.69 ns
Odd data setup
tDSE Dual lane mode 9, 10, 11 0.45 0.89 ns
Even data setup
tQSR Quad lane mode 9, 10, 11 0.45 0.63 ns
Data to rising clock setup
tQHF Quad lane mode 9, 10, 11 0,45 0.53 ns
Falling clock to data hold
SERIAL INTERFACE TIMING SPECIFICATIONS
fSCLK Input clock frequency fSCLK <= fINCLK 9, 10, 11 1 20 MHz
INCLK = ADCCLK
(ADC Rate Clock)
SCLK duty cycle 9, 10, 11 40/60 50/50 60/40 ns
tIH Input hold time 9, 10, 11 2.5 1 ns
tIS Input setup time 9, 10, 11 2.5 1 ns
tSENSC SCLK start time after SEN low 9, 10, 11 1.5 1 ns
tSCSEN SEN high after last SCLK rising edge 9, 10, 11 2.5 2 ns
tSENW SEN pulse width 9, 10, 11 8 6 ns
tOD Output delay time 9, 10, 11 10.54 11.6 ns
tHZ Data output to high Z 9, 10, 11 1.2 1.23 TSCLK
(1) This parameter is ensured by design and/or characterization and is not tested.