JAJSGF7G May 2010 – November 2018 LM98640QML-SP
PRODUCTION DATA.
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The LM98640QML-SP has a unique serial LVDS output format to protect data transfer during DLL upsets. The format provides a buffer on either side of the data word, this is accomplished by clocking a 14-bit word using a 16-bit clock rate. In the event of an upset that affects the DLL the output clock period could fluctuate; with no buffer for the data word this fluctuation could cause the loss of one or more of the data word bits, but because the LM98640QML-SP provides the buffer the fluctuation does not cause any data loss. The data can also be sent out in two modes: Dual or Quad Lane. The following sections describe these two modes.