JAJSGF7G May 2010 – November 2018 LM98640QML-SP
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This mode provides an LVDS output with a fixed value repeated continuously. The pattern starts asynchronously without CLPIN. The fixed value is set via the Test Pattern Value registers. The Test Pattern Value register is split into two registers the upper 8 bits of the test code in first register, and the lower 8 bits of the test code in the second. This is useful for system debugging of the LVDS link and receiver circuitry.