JAJSGF7G May 2010 – November 2018 LM98640QML-SP
PRODUCTION DATA.
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To read to the serial registers using the four wire interface, the timing diagram shown in Figure 27 must be met. Reading the registers takes two cycles. To start the first cycle, SEN is toggled low. At the rising edge of the first clock, the master should assume control of the SDI pin and begin issuing the read command. The read command is built of a "read" bit (1), device address bit (0), six bit register address, and eight "don't care" bits. SDI is clocked into the LM98640QML-SP at the rising edge of SCLK. SEN is toggled high for a delay of at least tSENW (see Figure 28). The second cycle begins when SEN is toggled low. The LM98640QML-SP assumes control of the SDO pin during the first eight clocks of the cycle. During this period, data is clocked out of the device at the rising edge of SCLK. The eight bit value clocked out is the contents of the previously addressed register. The next command can be sent on the SDI pin simultaneously during this second cycle. When SEN toggles high, the register is not written to, but its contents are staged to be outputted at the beginning of the next command.