SNAS254B October   2006  – April 2017 LM98714

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 AC Timing Specifications
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Clock Introduction
      2. 7.3.2  Modes of Operation
        1. 7.3.2.1 Mode 3 - Three Channel Input/Synchronous Pixel Sampling
        2. 7.3.2.2 Mode 2 - Two Channel Input/Synchronous Pixel Sampling
        3. 7.3.2.3 Mode 1a - One Channel Input/One, Two, Three, Four, or Five Color Sequential Line Sampling
        4. 7.3.2.4 Mode 1b - One Channel Input Per Line/Sequential Line (Input) Sampling/Three Channel Processing
      3. 7.3.3  Input Bias and Clamping
        1. 7.3.3.1 CDS Mode
        2. 7.3.3.2 Input Source Follower Buffers
        3. 7.3.3.3 VCLP DAC
      4. 7.3.4  Coarse Pixel Phase Alignment
      5. 7.3.5  Internal Sample Timing
      6. 7.3.6  Automatic Black Level Correction Loop
        1. 7.3.6.1 Black Level Offset DAC
        2. 7.3.6.2 Black Level Clamp (BLKCLP)
        3. 7.3.6.3 Pixel Averaging
        4. 7.3.6.4 Target Black Level
        5. 7.3.6.5 Offset Integration
        6. 7.3.6.6 Line Averaging
      7. 7.3.7  Internal Timing Generation
        1. 7.3.7.1 Pix Signal Generator OR/NOR Modes
        2. 7.3.7.2 SH2 and SH3 Generation
      8. 7.3.8  CCD Timing Generator Master/Slave Modes
        1. 7.3.8.1 Master Timing Generator Mode
        2. 7.3.8.2 Slave Timing Generator Mode
      9. 7.3.9  LVDS Output Mode
        1. 7.3.9.1 LVDS Output Format
        2. 7.3.9.2 LVDS Output Timing Details
        3. 7.3.9.3 LVDS Control Bit Coding
        4. 7.3.9.4 LVDS Data Latency Diagrams
        5. 7.3.9.5 LVDS Test Modes
          1. 7.3.9.5.1 Test Mode 1 - Worst Case Transitions
          2. 7.3.9.5.2 Test Mode 2 - Ramp
          3. 7.3.9.5.3 Test Mode 3 - Fixed Output Data
      10. 7.3.10 CMOS Output Mode
        1. 7.3.10.1 CMOS Output Data Format
      11. 7.3.11 CMOS Output Data Latency Diagrams
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mode 3 - Three Channel Input/Synchronous Pixel Sampling
      2. 7.4.2 Mode 2 - Two Channel Input/Synchronous Pixel Sampling
      3. 7.4.3 Mode 1a - One Channel Input/One, Two, Three, Four, Or Five Color Sequential Line Sampling
      4. 7.4.4 Mode 1b - One Channel Color Input Per Line/Sequential Line (Input) Sampling/Three Channel Processing
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 Writing To The Serial Registers
        2. 7.5.1.2 Reading The Serial Registers
        3. 7.5.1.3 Serial Interface Timing Details
    6. 7.6 Register Maps
      1. 7.6.1 Configuration Registers
      2. 7.6.2 Register Definition
  8. 8 Application and Implementation
    1. 8.1 Typical Application
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Device Support
        1. 9.1.1.1 Development Support
      2. 9.1.2 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Community Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DGG Package
48-Pin TSSOP
Top View
LM98714 20105302.gif

Pin Functions

PIN I/O(1) TYPE(1) RES.(1) DESCRIPTION
NO. NAME
1 CLK3 O D PU Configurable sensor control output.
2 CLK2 O D PD Configurable sensor control output.
3 CLK1 O D PU Configurable sensor control output.
4 SH O D PD Sensor - Shift or transfer control signal for CCD and CIS sensors.
5 RESET I D PU Active-low master reset. NC when function not being used.
6 SH_R I D PD External request for an SH pulse.
7 SDIO I/O D Serial Interface Data Input
8 SCLK I D PD Serial Interface shift register clock.
9 SEN I D PU Active-low chip enable for the Serial Interface.
10 AGND — P — Analog ground return.
11 VA — P — Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
12 VREFB O A — Bottom of ADC reference. Bypass with a 0.1μF capacitor to ground.
13 VREFT O A — Top of ADC reference. Bypass with a 0.1μF capacitor to ground.
14 VA — P — Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
15 AGND — P — Analog ground return.
16 VCLP IO A — Input Clamp Voltage. Normally bypassed with a 0.1μF, and a 4.7μF capacitor to AGND. An external reference voltage may be applied to this pin.
16 VCLP IO A — Input Clamp Voltage. Normally bypassed with a 0.1μF , and a 10μF capacitor to AGND. An external reference voltage may be applied to this pin.
17 VA — P — Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
18 AGND — P — Analog ground return.
19 OSR I A — Analog input signal. Typically sensor Red output AC-coupled through a capacitor.
20 AGND P — Analog ground return.
21 OSG I A — Analog input signal. Typically sensor Green output AC-coupled through a capacitor.
22 AGND P — Analog ground return.
23 OSB I A — Analog input signal. Typically sensor Blue output AC-coupled through a capacitor.
24 AGND — P — Analog ground return.
25 DGND — P — Digital ground return.
26 VR — P — Power supply input for internal voltage reference generator. Bypass this supply pin with a 0.1μF capacitor.
27 DVB O D — Digital Core Voltage bypass. Not an input. Bypass with 0.1μF capacitor to DGND.
28 INCLK+ I D — Clock Input. Non-Inverting input for LVDS clocks or CMOS clock input. CMOS clock is selected when pin 29 is held at DGND, otherwise clock is configured for LVDS operation.
29 INCLK- I D — Clock Input. Inverting input for LVDS clocks, connect to DGND for CMOS clock.
30 DOUT7/ O D — Bit 7 of the digital video output bus in CMOS Mode, LVDS Frame Clock+ in LVDS Mode.
TXCLK+
31 DOUT6/ O D — Bit 6 of the digital video output bus in CMOS Mode, LVDS Frame Clock- in LVDS Mode.
TXCLK-
32 DOUT5/ O D — Bit 5 of the digital video output bus in CMOS Mode, LVDS Data Out2+ in LVDS Mode.
TXOUT2+
33 DOUT4/ O D — Bit 4 of the digital video output bus in CMOS Mode, LVDS Data Out2- in LVDS Mode.
TXOUT2-
34 DOUT3/ O D — Bit 3 of the digital video output bus in CMOS Mode, LVDS Data Out1+ in LVDS Mode.
TXOUT1+
35 DOUT2/ O D — Bit 2 of the digital video output bus in CMOS Mode, LVDS Data Out1- in LVDS Mode.
TXOUT1-
36 DOUT1/ O D — Bit 1 of the digital video output bus in CMOS Mode, LVDS Data Out0+ in LVDS Mode.
TXOUT0+
37 DOUT0/ O D — Bit 0 of the digital video output bus in CMOS Mode, LVDS Data Out0- in LVDS Mode.
TXOUT0-
38 DGND — P — Digital ground return.
39 VD — P — Power supply for the digital circuits. Bypass this supply pin with 0.1μF capacitor. A single 4.7μF capacitor should be used between the supply and the VD, VR and VC pins.
40 CLKOUT/
CLK10		 O D PD Output clock for registering output data when using CMOS outputs, or configurable sensor control output.
41 CLK9 O D PD Configurable sensor control output.
42 CLK8 O D PD Configurable sensor control output.
43 CLK7 O D PD Configurable sensor control output.
44 CLK6 O D PU Configurable sensor control output.
45 CLK5 O D PD Configurable sensor control output.
46 DGND — P — Digital ground return.
47 VC — P — Power supply for the sensor control outputs. Bypass this supply pin with 0.1μF capacitor.
48 CLK4 O D PD Configurable sensor control output.
(1) I = Input, O = Output, IO = Bi-directional, P = Power, D = Digital, A = Analog, PU = Pullup with an internal resistor, PD = Pulldown with an internal resistor.