JAJSBE5D March   1998  – February 2024 LMC660 , LMC662

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information LMC662
    5. 5.5 Thermal Information LMC660
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Amplifier Topology
      2. 6.1.2 Compensating Input Capacitance
      3. 6.1.3 Capacitive Load Tolerance
      4. 6.1.4 Bias Current Testing
    2. 6.2 Typical Applications
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
        1. 6.3.1.1 Printed Circuit Board Layout for High-Impedance Work
  8. 7Device and Documentation Support
    1. 7.1 ドキュメントの更新通知を受け取る方法
    2. 7.2 サポート・リソース
    3.     Trademarks
    4. 7.3 静電気放電に関する注意事項
    5. 7.4 用語集
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.1.4 Bias Current Testing

The test method of Figure 6-5 is appropriate for bench-testing bias current with reasonable accuracy. To understand the circuit operation, first close switch S2 momentarily. When S2 is opened, then:

Equation 8. Ib-= dVOUTdt ×C2
GUID-046C9739-68AE-45C2-80FA-4FE1CB06D6A9-low.pngFigure 6-5 Simple Input Bias Current Test Circuit

A recommended capacitor for C2 is a 5pF or 10pF silver mica, NPO ceramic, or air-dielectric. When determining the magnitude of Ib−, take into account the leakage of the capacitor and socket. Leave switch S2 shorted most of the time, or else the dielectric absorption of the capacitor C2 can cause errors.

Similarly, if S1 is shorted momentarily (while leaving S2 shorted):

Equation 9. Ib+= dVOUTdt ×C1+Cx

where Cx is the stray capacitance at the noninverting input.