JAJSIG5C May   2019  – December 2024 LMG1025-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stage
      2. 6.3.2 Output Stage
      3. 6.3.3 Bias Supply and Under Voltage Lockout
      4. 6.3.4 Overtemperature Protection (OTP)
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Handling Ground Bounce
        2. 7.2.2.2 Creating Nanosecond Pulse
        3. 7.2.2.3 VDD and Overshoot
        4. 7.2.2.4 Operating at Higher Frequency
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Gate Drive Loop Inductance and Ground Connection
      2. 9.1.2 Bypass Capacitor
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 Trademarks
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DEE|6
サーマルパッド・メカニカル・データ

5.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tstartStartup Time, VDD rising above UVLOIN- = GND, IN+ = VDD , VDD rising above 4.4 V to OUTH rising4078µs
tshut-offULVO fallingIN- = GND, IN+ = VDD , VDD falling below 3.9 V to OUTH falling0.72.53.5µs
tpd, rPropagation delay, turn onIN- = 0 V, IN+ to OUTH, 100-pF load1.52.64.1ns
tpd, fPropagation delay, turn offIN- = 0 V, IN+ to OUTL, 100-pF load1.82.94.4ns
ΔtpdPulse positive distrortion, (tpd, f - tpd, r)0300610ps
triseOutput rise time0Ω series 220 pF load(1)650ps
tfallOutput fall time0Ω series 220 pF load(1)850ps
tminMinimum input pulse width that changes output state0Ω series 220 pF load(1)1.25ns
(1) Rise and fall time calcuated as time from 20% of the gate voltage to 80% of the gate voltage of the GaN FET.