JAJSLV7A
October 2022 – December 2022
LMG2610
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Typical Characteristics
7
Parameter Measurement Information
7.1
GaN Power FET Switching Parameters
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
GaN Power FET Switching Capability
8.3.2
Turn-On Slew-Rate Control
8.3.3
Current-Sense Emulation
8.3.4
Bootstrap Diode Function
8.3.5
Input Control Pins (EN, INL, INH)
8.3.6
INL - INH Interlock
8.3.7
AUX Supply Pin
8.3.7.1
AUX Power-On Reset
8.3.7.2
AUX Under-Voltage Lockout (UVLO)
8.3.8
BST Supply Pin
8.3.8.1
BST Power-On Reset
8.3.8.2
BST Under-Voltage Lockout (UVLO)
8.3.9
Over-Current Protection
8.3.10
Over-Temperature Protection
8.3.11
Fault Reporting
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Turn-On Slew-Rate Design
9.2.2.2
Current-Sense Design
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.1.1
Solder-Joint Stress Relief
9.4.1.2
Signal-Ground Connection
9.4.1.3
CS Pin Signal
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
Receiving Notification of Documentation Updates
10.3
サポート・リソース
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RRG|40
サーマルパッド・メカニカル・データ
発注情報
jajslv7a_oa
jajslv7a_pm
6.7
Typical Characteristics
Figure 6-1
Low-Side Normalized On-Resistance vs Junction Temperature
Figure 6-3
Low-Side Output Capacitance vs Drain-Source Voltage
Figure 6-5
High-Side Output Capacitance vs Drain-Source Voltage
Figure 6-7
Low-Side Drain Current Turn-On Delay Time vs Junction Temperature
Figure 6-9
Low-Side Turn-On Rise Time vs Junction Temperature
Figure 6-11
Low-Side Turn-Off Delay Time vs Junction Temperature
Figure 6-13
High-Side Turn-On Delay Time vs Junction Temperature
Figure 6-15
High-Side Turn-On Slew Rate vs Junction Temperature
Figure 6-17
AUX Standby Current vs Junction Temperature
INL = 5 V
Figure 6-19
AUX Quiescent Current vs Junction Temperature
INH = 0 V
Figure 6-21
BST Quiescent Current vs Junction Temperature
Figure 6-23
BST Operating Current vs Junction Temperature
Figure 6-2
High-Side Normalized On-Resistance vs Junction Temperature
Figure 6-4
Low-Side Output Capacitance Stored Energy vs Drain-Source Voltage
Figure 6-6
High-Side Output Capacitance Stored Energy vs Drain-Source Voltage
Figure 6-8
Low-Side Turn-On Delay Time vs Junction Temperature
Figure 6-10
Low-Side Turn-On Slew Rate vs Junction Temperature
Figure 6-12
High-Side Drain Current Turn-On Delay Time vs Junction Temperature
Figure 6-14
High-Side Turn-On Rise Time vs Junction Temperature
Figure 6-16
High-Side Turn-Off Delay Time vs Junction Temperature
INL = 0 V
Figure 6-18
AUX Quiescent Current vs Junction Temperature
Figure 6-20
AUX Operating Current vs Frequency
INH = 5 V
Figure 6-22
BST Quiescent Current vs Junction Temperature