JAJSLV7A October   2022  – December 2022 LMG2610

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 GaN Power FET Switching Parameters
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  GaN Power FET Switching Capability
      2. 8.3.2  Turn-On Slew-Rate Control
      3. 8.3.3  Current-Sense Emulation
      4. 8.3.4  Bootstrap Diode Function
      5. 8.3.5  Input Control Pins (EN, INL, INH)
      6. 8.3.6  INL - INH Interlock
      7. 8.3.7  AUX Supply Pin
        1. 8.3.7.1 AUX Power-On Reset
        2. 8.3.7.2 AUX Under-Voltage Lockout (UVLO)
      8. 8.3.8  BST Supply Pin
        1. 8.3.8.1 BST Power-On Reset
        2. 8.3.8.2 BST Under-Voltage Lockout (UVLO)
      9. 8.3.9  Over-Current Protection
      10. 8.3.10 Over-Temperature Protection
      11. 8.3.11 Fault Reporting
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Turn-On Slew-Rate Design
        2. 9.2.2.2 Current-Sense Design
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Solder-Joint Stress Relief
        2. 9.4.1.2 Signal-Ground Connection
        3. 9.4.1.3 CS Pin Signal
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • RRG|40
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

Figure 5-1 RRG Package, 40-Pin VQFN (Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
NC1 1, 13 NC Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally connected to DH.
DH 2-12 P High-side GaN FET drain. Internally connected to NC1.
SW 14-16 P GaN FET half-bridge switch node between the high-side GaN FET source and low-side GaN FET drain. Internally connected to PADH.
NC2 17, 21, 37 NC Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally connected to AGND, SL, and PADL.
SL 18-20, 22-27 P Low-side GaN FET source. Internally connected to AGND, PADL, and NC2.
EN 28 I Enable. Used to toggle between active and standby modes. The standby mode has reduced quiescent current to support converter light load efficiency targets. There is a forward biased ESD diode from EN to AUX so avoid driving EN higher than AUX.
INH 29 I High-side gate-drive control input. Referenced to AGND. Signal is level shifted internally to the high-side GaN FET driver. There is a forward biased ESD diode from INH to AUX so avoid driving INH higher than AUX.
INL 30 I Low-side gate-drive control input. Referenced to AGND. There is a forward biased ESD diode from INL to AUX so avoid driving INL higher than AUX.
AGND 31 GND Low-side analog ground. Internally connected to SL, PADL, and NC2.
CS 32 O Current-sense emulation output. Outputs 1 ma/A scaled replica of the low-side GaN FET current. Feed output current into a resistor to create a current sense voltage signal. Reference the resistor to the power supply controller IC local ground. This function replaces the external current-sense resistor that is used in series with the low-side FET.
NC3 33 NC Used to anchor QFN package to PCB. Pin must be soldered to a PCB landing pad. The PCB landing pad is non-solder mask defined pad and must not be physically connected to any other metal on the PCB. Pin not connected internally.
FLT 34 O Active-low fault output. Open-drain output that asserts during an over-temperature shut down.
AUX 35 P Auxiliary voltage rail. Low-side supply voltage. Connect a local bypass capacitor between AUX and AGND.
RDRVL 36 I Low-side drive strength control resistor. Set a resistance between RDRVL and AGND to program the low-side GaN FET turn-on slew rate.
BST 38 P Bootstrap voltage rail. High-side supply voltage. The bootstrap diode function between AUX and BST is internally provided. Connect an appropriately sized bootstrap capacitor between BST and SW. Recommend to make the SW connection using NC4 as a pass through connection to PADH (PADH = SW) as explained in the NC4 description.
RDRVH 39 I High-side drive strength control resistor. Set a resistance between RDRVH and SW to program the high-side GaN FET turn-on slew rate. Recommend to make the SW connection using NC4 as a pass through connection to PADH (PADH = SW) as explained in the NC4 description.
NC4 40 NC Pin is not functional. Pin is high impedance and referenced to SW. Recommend to connect pin to PADH (PADH = SW) to use as convenient connection for the BST bypass capacitor and the RDRVH resistor. See the example board layout in the Layout Example section.
PADH 41 TP High-side thermal pad. Internally connected to SW. All the SW current can be conducted with PADH (PADH = SW).
PADL 42 TP Low-side thermal pad. Internally connected to SL, AGND, and NC2. All the SL current can be conducted with PADL (PADL = SL).
(1) I = Input, O = Output, G = Ground, P = Power, NC = No Connect, TP = Thermal Pad.