JAJSLV7A October   2022  – December 2022 LMG2610

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 GaN Power FET Switching Parameters
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  GaN Power FET Switching Capability
      2. 8.3.2  Turn-On Slew-Rate Control
      3. 8.3.3  Current-Sense Emulation
      4. 8.3.4  Bootstrap Diode Function
      5. 8.3.5  Input Control Pins (EN, INL, INH)
      6. 8.3.6  INL - INH Interlock
      7. 8.3.7  AUX Supply Pin
        1. 8.3.7.1 AUX Power-On Reset
        2. 8.3.7.2 AUX Under-Voltage Lockout (UVLO)
      8. 8.3.8  BST Supply Pin
        1. 8.3.8.1 BST Power-On Reset
        2. 8.3.8.2 BST Under-Voltage Lockout (UVLO)
      9. 8.3.9  Over-Current Protection
      10. 8.3.10 Over-Temperature Protection
      11. 8.3.11 Fault Reporting
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Turn-On Slew-Rate Design
        2. 9.2.2.2 Current-Sense Design
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Solder-Joint Stress Relief
        2. 9.4.1.2 Signal-Ground Connection
        3. 9.4.1.3 CS Pin Signal
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • RRG|40
サーマルパッド・メカニカル・データ
発注情報

8.3.8.2 BST Under-Voltage Lockout (UVLO)

The BST UVLO voltage is with respect to the SW pin. The BST UVLO only controls the high-side GaN power FET. The BST UVLO does not control the low-side GaN power FET. The BST UVLO consists of two separate UVLO functions to create a two-level BST UVLO. The upper BST UVLO is called the BST Turn-On UVLO and only controls if the high-side GaN power FET is turned on. The lower BST UVLO is called the BST Turn-Off UVLO and only controls if the high-side GaN power FET is turned off after the high-side GaN power FET is turned on. The operation of the two-level UVLO is not the same as a single UVLO with wide hysteresis.

Figure 8-4 shows the BST UVLO operation. The BST Turn-On UVLO prevents the high-side GaN power FET from turning on at a INH logic-high rising edge if the BST-to-SW voltage is below the BST Turn-On UVLO voltage - INH pulses #1, #2, and #5. After the high-side GaN power FET is successfully turned-on, the BST Turn-On UVLO is ignored and the BST Turn-Off UVLO output is watched for the remainder of the INH logic-high pulse - INH pulses #3, #4, and #6. The BST Turn-Off UVLO turns off the high-side GaN power FET for the remainder of the INH logic-high pulse if the BST-to-SW voltage falls below the BST Turn-Off UVLO voltage - INH pulse #6.



Figure 8-4 BST UVLO Operation

The effective voltage hysteresis of the two-level BST UVLO is the difference between the upper and lower BST UVLO voltages. A single-level BST UVLO can be implemented with the same hysteresis but allows subsequent high-side GaN power FET turn on anywhere in the hysteresis range. The two-level UVLO design prevents any turn on in the hysteresis range. A single-level BST UVLO would allow INH pulse #5 to turn on the high-side GaN power FET.

The two-level BST UVLO allows a wide hysteresis while making sure the BST-to-SW capacitor is adequately charged at the beginning of every INH pulse. The wide hysteresis allows a smaller BST-to-SW capacitor to be used which is useful for faster high-side start-up time. The adequate capacitor charge at the beginning of the INH pulse helps make sure the high-side GaN power FET is not turned-off early in the INH pulse which can create undesired spike voltages in the converter.