JAJSLV7A October   2022  – December 2022 LMG2610

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 GaN Power FET Switching Parameters
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  GaN Power FET Switching Capability
      2. 8.3.2  Turn-On Slew-Rate Control
      3. 8.3.3  Current-Sense Emulation
      4. 8.3.4  Bootstrap Diode Function
      5. 8.3.5  Input Control Pins (EN, INL, INH)
      6. 8.3.6  INL - INH Interlock
      7. 8.3.7  AUX Supply Pin
        1. 8.3.7.1 AUX Power-On Reset
        2. 8.3.7.2 AUX Under-Voltage Lockout (UVLO)
      8. 8.3.8  BST Supply Pin
        1. 8.3.8.1 BST Power-On Reset
        2. 8.3.8.2 BST Under-Voltage Lockout (UVLO)
      9. 8.3.9  Over-Current Protection
      10. 8.3.10 Over-Temperature Protection
      11. 8.3.11 Fault Reporting
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Turn-On Slew-Rate Design
        2. 9.2.2.2 Current-Sense Design
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Solder-Joint Stress Relief
        2. 9.4.1.2 Signal-Ground Connection
        3. 9.4.1.3 CS Pin Signal
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • RRG|40
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

1) Symbol definitions: VDS(ls) = SW to SL voltage; IDS(ls) = SW to SL current; VDS(hs) = DH to SW voltage;  ID(hs) = DH to SW current;  2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; -40 °C ≤ TJ ≤ 125 °C; 10 ≤ VAUX ≤ 26; 7.5 ≤ VBST_SW ≤ 26; VEN = 5 V; VINL = 0 V; VINH = 0 V; RRDRVL = 0 Ω; RRDRVH_SW = 0 Ω; RCS = 100 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOW-SIDE GAN POWER FET
RDS(on)(ls) Drain-source (SW to SL)  on resistance VINL = 5 V, ID(ls) = 3 A, TJ = 25°C     170 mΩ
VINL = 5 V, ID(ls) = 3 A, TJ = 125°C 325
VSD(ls) Source-drain (SL to SW) third-quadrant voltage SL to SW current = 0.1 A -1.9 V
SL to SW current = 1 A -2.6
IDSS(ls) Drain (SW to SL) leakage current VDS(hs) = 0 V, VDS(ls) = 650 V, TJ = 25 °C 2 µA
VDS(hs) = 0 V, VDS(ls) = 650 V, TJ = 125 °C 10
QOSS(ls) Output (SW to SL) charge VDS(hs) = 0 V, VDS(ls) = 400 V 19.7 nC
COSS(ls) Output (SW to SL) capacitance 22 pF
EOSS(ls) Output (SW to SL) capacitance stored energy 2.32 µJ
COSS,er(ls) Energy related effective output (SW to SL) capacitance 29 pF
COSS,tr(ls) Time related effective output (SW to SL) capacitance VDS(hs) = 0 V, VDS(ls) = 0 V to 400 V 49.2 pF
QRR(ls) Reverse recovery charge 0 nC
HIGH-SIDE GAN POWER FET
RDS(on)(hs) Drain-source (DH to SW) on resistance VINH = 5 V, ID(hs) = 1.75 A, TJ = 25°C 248 mΩ
VINH = 5 V, ID(hs) = 1.75 A, TJ = 125°C 470
VSD(hs) Source-drain (SW to DH) third-quadrant voltage SW to DH current = 0.1 A -2 V
SW to DH current = 1 A -2.7
IDSS(hs) Drain (DH to SW) leakage current VDS(ls) = 0 V, VDS(hs) = 650 V,  TJ = 25 °C 1.4 µA
VDS(ls) = 0 V, VDS(hs) = 650 V,  TJ = 125 °C 7
QOSS(hs) Output (DH to SW) charge  VDS(ls) = 0 V, VDS(hs) = 400 V 15.51 nC
COSS(hs) Output (DH to SW) capacitance 22.4 pF
EOSS(hs) Output (DH to SW) capacitance stored energy 2.15 µJ
COSS,er(hs) Energy related effective output (DH to SW) capacitance 26.9 pF
COSS,tr(hs) Time related effective output (DH to SW) capacitance VDS(ls) = 0 V, VDS(hs) = 0 V to 400 V 38.78 pF
QRR(hs) Reverse recovery charge 0 nC
LOW-SIDE OVERCURRENT PROTECTION
IT(OC)(ls) Overcurrent fault – threshold current 5.4 5.9 6.4 A
HIGH-SIDE OVERCURRENT PROTECTION
IT(OC)(hs) Overcurrent fault – threshold current 3 3.5 4 A
BOOTSTRAP RECTIFIER
RDS(on) AUX to BST on resistance VINL = 5 V, VAUX_BST = 1 V, TJ = 25°C  8 Ω
VINL = 5 V, VAUX_BST = 1 V, TJ = 125°C  14
AUX to BST current limit VINL = 5 V, VAUX_BST = 7 V 210 240 270 mA
BST to AUX reverse current blocking threshold VINL = 5 V 15 mA
CS
Current sense gain (ICS(src) / ID(LS)) VINL = 5 V, 0 A ≤ ID(ls) < IT(OC)(ls), 0 V ≤ VCS ≤ 2 V 1 mA/A
Current sense input offset current VINL = 5 V, 0 A ≤ ID(ls) < IT(OC)(ls), 0 V ≤ VCS ≤ 2 V –50 50 mA
Initial held output after overcurrent fault occurs while INL remains high VINL = 5 V, 0 V ≤ VCS ≤ 2 V 7 mA
ICS(src)(OC)(final) Final held output after overcurrent fault occurs while INL remains high VINL = 5 V, 0 V ≤ VCS ≤ 2 V 10 12 15.5 mA
Output clamp voltage VINL = 5 V, ID(ls) = 5 A, CS sinking 5 mA from external source 2.5 V
EN, INL, INH
VIT+ Positive-going input threshold voltage 1.7 2.45 V
VIT– Negative-going input threshold voltage 0.7 1.3 V
Input threshold voltage hysteresis 1 V
Pull-down resistance 0 V ≤ VPIN ≤ 3 V 200 400 600 kΩ
Pull-down current VAUX = 26 V; 10 V ≤ VPIN ≤ 26 V  10 µA
OVER-TEMPERATURE PROTECTION
Temperature fault – postive-going threshold temperature 150 °C
Temperature fault – negative-going threshold temperature 130 °C
Temperature fault – threshold temperature hysteresis 20 °C
FLT
Low-level output voltage FLT sinking 1mA while asserted 200 mV
Off-state current VFLT = VAUX while de-asserted 1 µA
AUX
VAUX,T+(UVLO) UVLO – positive-going threshold voltage 8.9 9.3 9.7 V
UVLO – negative-going threshold voltage 8.6 9.0 9.4 V
UVLO – threshold voltage hysteresis 250 mV
Standby quiescent current VEN = 0 V 50 80 µA
Quiescent current 250 370 µA
VINL = 5 V, ID(ls) = 0 A 1370 µA
Operating current  VINL = 0 V or 5 V, VDS(ls) = 0 V, fINL = 500 kHz, ID(ls) = 0 A 3.1 mA
BST
VBST_SW,T+(UVLO) VBST_SW UVLO for FET to turn on – positive-going threshold voltage 6.7 7 7.3 V
VBST_SW UVLO for FET to stay on– negative-going threshold voltage 4.8 5.1 5.4 V
Quiescent current 65 100 µA
VINH = 5 V 330
Operating current VINH = 0 V or 5 V, VDS(hs) = 0 V; fINH = 500 kHz 1.2 mA